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ARM64: dts: rockchip: rk3399: assigned clk_uart4_src parent to PPLL

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clk_uart4_src default parent is 24M,does not satisfy the
fractional divider must set that denominator is 20 times
larger than numerator.

Change-Id: I21fd9866794e052414a6fdf1d64840ac2a0bb8f2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2017-09-20 10:05:51 +08:00
parent 1b523997b3
commit a8cf408589
1 changed files with 2 additions and 2 deletions
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4
arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi
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@@ -75,8 +75,8 @@
};
&uart4 {
assigned-clocks = <&cru SCLK_UART_SRC>;
assigned-clock-parents = <&cru PLL_GPLL>;
assigned-clocks = <&pmucru SCLK_UART4_SRC>;
assigned-clock-parents = <&pmucru PLL_PPLL>;
};
&spdif {