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drm/rockchip: analogix_dp: Add support for RK3368

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Add eDP controller support for RK3368 SoC.
RK3368 eDP controller is similar to the RK3288.

Change-Id: I738ddf122776081cf41adef2921644ddfc6e07dd
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2019-07-01 14:13:17 +08:00
committed by Tao Huang
parent 19d3ef2a43
commit a9b97c9f5e
6 changed files with 15 additions and 6 deletions
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1
Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
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@@ -5,6 +5,7 @@ Required properties for dp-controller:
platform specific such as:
* "samsung,exynos5-dp"
* "rockchip,rk3288-dp"
* "rockchip,rk3368-edp"
* "rockchip,rk3399-edp"
-reg:
physical base address of the controller and length

1
Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
View File

@@ -3,6 +3,7 @@ Rockchip RK3288 specific extensions to the Analogix Display Port
Required properties:
- compatible: "rockchip,rk3288-dp",
"rockchip,rk3368-edp",
"rockchip,rk3399-edp";
- reg: physical base address of the controller and length

5
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
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@@ -1511,11 +1511,8 @@ static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
switch (dp->plat_data->dev_type) {
case RK3288_DP:
case RK3368_EDP:
case RK3399_EDP:
/*
* Like Rk3288 DisplayPort TRM indicate that "Main link
* containing 4 physical lanes of 2.7/1.62 Gbps/lane".
*/
video_info->max_link_rate = 0x0A;
video_info->max_lane_count = 0x04;
break;

3
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
View File

@@ -94,7 +94,8 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
reg = REF_CLK_24M;
if (dp->plat_data->dev_type == RK3288_DP)
if (dp->plat_data->dev_type == RK3288_DP ||
dp->plat_data->dev_type == RK3368_EDP)
reg ^= REF_CLK_MASK;
analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_1, reg);

8
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
View File

@@ -212,6 +212,9 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
int ret;
u32 val;
if (!dp->data->lcdsel_grf_reg)
return;
ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
if (ret < 0)
return;
@@ -539,6 +542,10 @@ static const struct rockchip_dp_chip_data rk3399_edp = {
.chip_type = RK3399_EDP,
};
static const struct rockchip_dp_chip_data rk3368_edp = {
.chip_type = RK3368_EDP,
};
static const struct rockchip_dp_chip_data rk3288_dp = {
.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
.lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
@@ -548,6 +555,7 @@ static const struct rockchip_dp_chip_data rk3288_dp = {
static const struct of_device_id rockchip_dp_dt_ids[] = {
{.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
{.compatible = "rockchip,rk3368-edp", .data = &rk3368_edp },
{.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
{}
};

3
include/drm/bridge/analogix_dp.h
View File

@@ -18,12 +18,13 @@ struct analogix_dp_device;
enum analogix_dp_devtype {
EXYNOS_DP,
RK3288_DP,
RK3368_EDP,
RK3399_EDP,
};
static inline bool is_rockchip(enum analogix_dp_devtype type)
{
return type == RK3288_DP || type == RK3399_EDP;
return type == RK3288_DP || type == RK3399_EDP || type == RK3368_EDP;
}
struct analogix_dp_plat_data {