Merge commit 'f133c251b13655afb15cba35920f02c147a62f9a'

* commit 'f133c251b13655afb15cba35920f02c147a62f9a': (25 commits)
  drm/rockchip: dsi2: add support split mode
  ARM: configs: add rv1126b cvr fastboot configuration
  arm64: dts: rockchip: rk3588: remove unnecessary references to rkcif_mmu
  arm64: dts: rockchip: rk3576: remove unnecessary references to rkcif_mmu
  media: i2c: os12d40 fixes error bayer pattern when mirror/flip change
  drm/rockchip: vop2: use rkiommu 1.0 for rk3576 reserved plane mode
  drm/rockchip: vop2: add support reserved plane display
  dt-bindings: display: add Fast Boot Display mode define
  ARM: configs: rv1126b-cvr add cvr configuration
  arm64: dts: rockchip: rk3576-vehicle-evb-v20-maxim-max96712-dphy0-ox03c10.dtsi: enable multi raw sensor mode
  arm64: dts: rockchip: add rk3576-vehicle-evb-v20-maxim-max96712-dphy0-ox03c10.dtsi
  arm64: configs: rk3576_vehicle.config: add CONFIG_VIDEO_MAXIM_CAM_OX03C10=y
  media: i2c: maxim: remote: add ox03c10 sensor driver
  arm64: dts: rockchip: rk3588-vehicle-evb: Add max96749+max96772 2560x1600 resolution case
  arm64: configs: rk3588_vehicle.config: enable CONFIG_PWM_R7F701
  pwm: add support for r7f701
  mfd: display-serdes: Add max96772 gpio interface control and read dpcd information
  mfd: display-serdes: Add support for max96749
  arm64: dts: rockchip: Add hyn touchscreen support
  arm64: dts: rockchip: add rv1126b-evb2-v10-aov-dual-cam.dts and update Makefile
  ...

Change-Id: I4519ccb3cae351f2368cdb85b9df8ea355439c1f

arch/arm64/boot/dts/rockchip/Makefile

@@ -385,6 +385,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-fastboot-spi-nand.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-fastboot-spi-nor.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-spi-nor.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-aov-dual-cam.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-mcu-k350c4516t.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-rgb-Q7050ITH2641AA1T.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-sii9022-bt1120-to-hdmi.dtb

arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts

@@ -919,6 +919,26 @@
 
 		power-supply = <&vcc3v3_lcd>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+
+		power-supply = <&vcc3v3_lcd>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2c5 {
@@ -1012,6 +1032,22 @@
 				<0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
 				<0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	sdio-pwrseq {

arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi

@@ -505,6 +505,29 @@
 		 */
 		power-supply = <&vcc3v3_lcd_n>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		/*
+		 * power-supply should switche to vcc3v3_lcd1_n
+		 * when mipi panel is connected to dsi1.
+		 */
+		power-supply = <&vcc3v3_lcd_n>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &jpegd {
@@ -526,6 +549,22 @@
 				<0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
 				<0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 };
 

arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dtsi

@@ -492,6 +492,29 @@
 		 */
 		power-supply = <&vcc3v3_lcd_n>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		/*
+		 * power-supply should switche to vcc3v3_lcd1_n
+		 * when mipi panel is connected to dsi1.
+		 */
+		power-supply = <&vcc3v3_lcd_n>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &pinctrl {
@@ -507,6 +530,22 @@
 				<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
 				<0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 };
 

arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi

@@ -227,6 +227,29 @@
 	power-supply = <&vcc3v3_lcd_n>;
 };
 
+&hynitron {
+	compatible = "hyn,3240";
+	reg = <0x5a>;
+	/*
+	 * power-supply should switche to vcc3v3_lcd1_n
+	 * when mipi panel is connected to dsi1.
+	 */
+	power-supply = <&vcc3v3_lcd_n>;
+
+	pinctrl-names = "ts_active","ts_suspend";
+	pinctrl-0 = <&ts_int_active &ts_reset_active>;
+	pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+	irq-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+
+	max-touch-number = <5>;
+	display-coords = <0 0 1080 1920>;
+	pos-swap = <0>;
+	posx-reverse = <0>;
+	posy-reverse = <0>;
+};
+
 &mdio0 {
 	rgmii_phy: phy@1 {
 		compatible = "ethernet-phy-ieee802.3-c22";
@@ -262,6 +285,22 @@
 				<0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
 				<0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rk3562-toybrick.dtsi

@@ -293,6 +293,29 @@
 		interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
 		wakeup-source;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		/*
+		 * power-supply should switche to vcc3v3_lcd1_n
+		 * when mipi panel is connected to dsi1.
+		 */
+		power-supply = <&vcc3v3_lcd_n>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &mdio0 {
@@ -342,6 +365,22 @@
 				<0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
 				<0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	sdio-pwrseq {

arch/arm64/boot/dts/rockchip/rk3566-evb-mipitest-v10.dtsi

@@ -227,6 +227,11 @@
 	power-supply = <&vcc3v3_lcd0_n>;
 };
 
+&hynitron {
+	status = "disabled";
+	power-supply = <&vcc3v3_lcd0_n>;
+};
+
 &hdmi {
 	status = "disabled";
 };

arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dtsi

@@ -226,6 +226,10 @@
 	power-supply = <&vcc3v3_lcd0_n>;
 };
 
+&hynitron {
+	power-supply = <&vcc3v3_lcd0_n>;
+};
+
 &i2c2 {
 	status = "okay";
 	pinctrl-names = "default";

arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10-eink.dts

@@ -150,6 +150,10 @@
 	status = "disabled";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &hdmi {
 	status = "disabled";
 };

arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dtsi

@@ -364,6 +364,10 @@
 	power-supply = <&vcc3v3_lcd0_n>;
 };
 
+&hynitron {
+	power-supply = <&vcc3v3_lcd0_n>;
+};
+
 &mipi_csi2 {
 	status = "okay";
 

arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi

@@ -188,6 +188,10 @@
 	power-supply = <&vcc3v3_lcd0_n>;
 };
 
+&hynitron {
+	power-supply = <&vcc3v3_lcd0_n>;
+};
+
 &i2c2 {
 	status = "okay";
 	pinctrl-0 = <&i2c2m1_xfer>;

arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dtsi

@@ -172,6 +172,10 @@
 	power-supply = <&vcc3v3_lcd0_n>;
 };
 
+&hynitron {
+	power-supply = <&vcc3v3_lcd0_n>;
+};
+
 &i2c5 {
 	status = "disabled";
 };

arch/arm64/boot/dts/rockchip/rk3566pro-evb2-lp4x-v10.dtsi

@@ -396,6 +396,10 @@
 	power-supply = <&vcc3v3_lcd0_n>;
 };
 
+&hynitron {
+	power-supply = <&vcc3v3_lcd0_n>;
+};
+
 &mipi_csi2 {
 	status = "okay";
 

arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2dsi-ddr4-v10.dts

@@ -15,6 +15,13 @@
 	goodix,irq-gpio = <&gpio0 RK_PA4 IRQ_TYPE_LEVEL_LOW>;
 };
 
+&hynitron {
+	status = "okay";
+	power-supply = <&vcc3v3_lcd0_n>;
+	reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+	irq-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+};
+
 &i2c2_rk628 {
 	panel-backlight = <&backlight>;
 	panel-power-supply = <&vcc3v3_lcd0_n>;

arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2dsi-dual-ddr4-v10.dts

@@ -12,6 +12,10 @@
 	status = "disabled";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c2_rk628 {
 	panel-backlight = <&backlight>;
 	panel-power-supply = <&vcc3v3_lcd0_n>;

arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2gvi-ddr4-v10.dts

@@ -16,6 +16,10 @@
 	status = "disabled";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c2_rk628 {
 		panel-backlight = <&backlight>;
 		panel-power-supply = <&vcc3v3_lcd0_n>;

arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2lvds-ddr4-v10.dts

@@ -12,6 +12,10 @@
 	status = "disabled";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c2_rk628 {
 	panel-backlight = <&backlight>;
 	panel-power-supply = <&vcc3v3_lcd0_n>;

arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2lvds-dual-ddr4-v10.dts

@@ -16,6 +16,10 @@
 	status = "disabled";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c2_rk628 {
 		panel-backlight = <&backlight>;
 		panel-power-supply = <&vcc3v3_lcd0_n>;

arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2dsi-ddr4-v10.dts

@@ -46,6 +46,13 @@
 	goodix,irq-gpio = <&gpio0 RK_PA4 IRQ_TYPE_LEVEL_LOW>;
 };
 
+&hynitron {
+	status = "okay";
+	power-supply = <&vcc3v3_lcd0_n>;
+	reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+	irq-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+};
+
 &i2c2_rk628 {
 		panel-backlight = <&backlight>;
 		panel-power-supply = <&vcc3v3_lcd0_n>;

arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2gvi-ddr4-v10.dts

@@ -47,6 +47,10 @@
 	status = "disabled";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c2_rk628 {
 		panel-backlight = <&backlight>;
 		panel-power-supply = <&vcc3v3_lcd0_n>;

arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2hdmi-ddr4-v10.dts

@@ -15,6 +15,10 @@
 	status = "disabled";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c2_rk628 {
 		assigned-clocks = <&pmucru CLK_WIFI>;
 		assigned-clock-rates = <24000000>;

arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2lvds-ddr4-v10.dts

@@ -47,6 +47,10 @@
 	status = "disabled";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c2_rk628 {
 		panel-backlight = <&backlight>;
 		panel-power-supply = <&vcc3v3_lcd0_n>;

arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2lvds-dual-ddr4-v10.dts

@@ -48,6 +48,10 @@
 	status = "disabled";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c2_rk628 {
 		panel-backlight = <&backlight>;
 		panel-power-supply = <&vcc3v3_lcd0_n>;

arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi

@@ -1380,6 +1380,24 @@
 		goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
 		goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2c5 {
@@ -1496,6 +1514,22 @@
 				<0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
 				<0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	sdio-pwrseq {

arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtsi

@@ -263,6 +263,10 @@
 	power-supply = <&vcc3v3_lcd0_n>;
 };
 
+&hynitron {
+	power-supply = <&vcc3v3_lcd0_n>;
+};
+
 &i2c4 {
 	status = "okay";
 

arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi

@@ -211,6 +211,10 @@
 	power-supply = <&vcc3v3_lcd0_n>;
 };
 
+&hynitron {
+	power-supply = <&vcc3v3_lcd0_n>;
+};
+
 &i2c3 {
 	status = "okay";
 

arch/arm64/boot/dts/rockchip/rk3568-evb5-ddr4-v10.dtsi

@@ -264,6 +264,10 @@
 	power-supply = <&vcc3v3_lcd0_n>;
 };
 
+&hynitron {
+	power-supply = <&vcc3v3_lcd0_n>;
+};
+
 &i2c3 {
 	clock-frequency = <400000>;
 	status = "okay";

arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dtsi

@@ -111,6 +111,10 @@
 	power-supply = <&vcc3v3_lcd0_n>;
 };
 
+&hynitron {
+	power-supply = <&vcc3v3_lcd0_n>;
+};
+
 &i2c2 {
 	status = "okay";
 	pinctrl-names = "default";

arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-mipi-tx0.dtsi

@@ -45,6 +45,25 @@
 		goodix,rst-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
 		goodix,irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_LEVEL_LOW>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		status = "okay";
+		reg = <0x5a>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &pwm14{
@@ -72,5 +91,21 @@
 				<4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>,
 				<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 };

arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10-camera.dtsi

@@ -44,6 +44,10 @@
 	status = "disabled";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &combphy0_us {
 	status = "okay";
 };

arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10.dtsi

@@ -49,6 +49,10 @@
 	status = "disabled";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c0 {
 	status = "okay";
 

arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-lp4x-v10.dtsi

@@ -49,6 +49,10 @@
 	status = "disabled";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c0 {
 	status = "okay";
 

arch/arm64/boot/dts/rockchip/rk3576-toybrick-d0-linux.dts

@@ -714,6 +714,26 @@
 		goodix,irq-gpio = <&gpio0 RK_PC5 IRQ_TYPE_LEVEL_LOW>;
 		power-supply = <&vcc3v3_lcd_n>;
 	};
+
+	hynitron: hynitron@5a {
+		status = "okay";
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc3v3_lcd_n>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2c1 {
@@ -1210,6 +1230,22 @@
 				<0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>,
 				<0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rk3576.dtsi

@@ -1444,7 +1444,6 @@
 	rkcif_dvp: rkcif-dvp {
 		compatible = "rockchip,rkcif-dvp";
 		rockchip,hw = <&rkcif>;
-		iommus = <&rkcif_mmu>;
 		status = "disabled";
 	};
 
@@ -1457,7 +1456,6 @@
 	rkcif_mipi_lvds: rkcif-mipi-lvds {
 		compatible = "rockchip,rkcif-mipi-lvds";
 		rockchip,hw = <&rkcif>;
-		iommus = <&rkcif_mmu>;
 		status = "disabled";
 	};
 
@@ -1488,7 +1486,6 @@
 	rkcif_mipi_lvds1: rkcif-mipi-lvds1 {
 		compatible = "rockchip,rkcif-mipi-lvds";
 		rockchip,hw = <&rkcif>;
-		iommus = <&rkcif_mmu>;
 		status = "disabled";
 	};
 
@@ -1519,7 +1516,6 @@
 	rkcif_mipi_lvds2: rkcif-mipi-lvds2 {
 		compatible = "rockchip,rkcif-mipi-lvds";
 		rockchip,hw = <&rkcif>;
-		iommus = <&rkcif_mmu>;
 		status = "disabled";
 	};
 
@@ -1550,7 +1546,6 @@
 	rkcif_mipi_lvds3: rkcif-mipi-lvds3 {
 		compatible = "rockchip,rkcif-mipi-lvds";
 		rockchip,hw = <&rkcif>;
-		iommus = <&rkcif_mmu>;
 		status = "disabled";
 	};
 
@@ -1581,7 +1576,6 @@
 	rkcif_mipi_lvds4: rkcif-mipi-lvds4 {
 		compatible = "rockchip,rkcif-mipi-lvds";
 		rockchip,hw = <&rkcif>;
-		iommus = <&rkcif_mmu>;
 		status = "disabled";
 	};
 

arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-ipc-6x-linux.dts

@@ -83,6 +83,10 @@
 	status = "disabled";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c6 {
 	status = "disabled";
 };

arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi

@@ -496,6 +496,25 @@
 		goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>;
 		power-supply = <&vcc3v3_lcd_n>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc3v3_lcd_n>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2c7 {
@@ -634,6 +653,22 @@
 				<0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>,
 				<0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rk3588-evb10.dtsi

@@ -503,6 +503,25 @@
 		goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>;
 		power-supply = <&vcc3v3_lcd_n>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc3v3_lcd_n>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2c5m3_xfer {
@@ -795,6 +814,22 @@
 				<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>,
 				<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-edp.dts

@@ -118,6 +118,10 @@
 	status = "okay";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c6 {
 	clock-frequency = <400000>;
 	status = "okay";

arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi

@@ -328,6 +328,25 @@
 		goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>;
 		power-supply = <&vcc3v3_lcd_n>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc3v3_lcd_n>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2c7 {
@@ -436,6 +455,22 @@
 				<0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>,
 				<0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp-linux.dts

@@ -87,6 +87,10 @@
 	status = "okay";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c5 {
 	clock-frequency = <400000>;
 	status = "okay";

arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp.dts

@@ -87,6 +87,10 @@
 	status = "okay";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c5 {
 	clock-frequency = <400000>;
 	status = "okay";

arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi

@@ -984,6 +984,25 @@
 		goodix,irq-gpio = <&gpio4 RK_PB1 IRQ_TYPE_LEVEL_LOW>;
 		power-supply = <&vcc3v3_lcd_n>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc3v3_lcd_n>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2c7 {
@@ -1103,6 +1122,22 @@
 				<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
 				<4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4.dtsi

@@ -268,6 +268,25 @@
 		goodix,irq-gpio = <&gpio0 RK_PC6 IRQ_TYPE_LEVEL_LOW>;
 		power-supply = <&vcc3v3_lcd_n>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc3v3_lcd_n>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2c8 {
@@ -383,6 +402,22 @@
 				<0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>,
 				<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rk3588-evb6-lp4.dtsi

@@ -341,6 +341,25 @@
 		goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>;
 		power-supply = <&vcc3v3_lcd_n>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc3v3_lcd_n>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2s5_8ch {
@@ -418,6 +437,22 @@
 				<0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>,
 				<0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dts

@@ -87,6 +87,10 @@
 	status = "disabled";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c6 {
 	status = "disabled";
 };

arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi

@@ -549,6 +549,25 @@
 		goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>;
 		power-supply = <&vcc3v3_lcd_n>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc3v3_lcd_n>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2c6 {
@@ -707,6 +726,22 @@
 				<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>,
 				<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dtsi

@@ -560,6 +560,24 @@
 		goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>;
 		power-supply = <&vcc3v3_lcd_n>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2c6 {
@@ -774,6 +792,22 @@
 				<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>,
 				<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rk3588-toybrick-edp-x0.dtsi

@@ -518,6 +518,24 @@
 		irq_gpio_number = <&gpio1 RK_PA6 IRQ_TYPE_LEVEL_LOW>;
 		rst_gpio_number = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2c7 {
@@ -649,6 +667,22 @@
 				<0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>,
 				<0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {
@@ -767,4 +801,3 @@
 &usbhost_dwc3_0 {
 	status = "disabled";
 };
-

arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi

@@ -519,6 +519,25 @@
 		irq_gpio_number = <&gpio1 RK_PA6 IRQ_TYPE_LEVEL_LOW>;
 		rst_gpio_number = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc3v3_lcd_n>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2c7 {
@@ -622,6 +641,22 @@
 				<0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>,
 				<0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi

@@ -813,6 +813,25 @@
 		goodix,irq-gpio = <&gpio4 RK_PB4 IRQ_TYPE_LEVEL_LOW>;
 		power-supply = <&vcc3v3_lcd_n>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc3v3_lcd_n>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2c3 {
@@ -892,6 +911,22 @@
 				<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
 				<4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dts

@@ -20,12 +20,16 @@
 };
 
 /*
- * The pins of gt1x and sii9022 are multiplexed
+ * The pins of gt1x/hynitron and sii9022 are multiplexed
  */
 &gt1x {
 	status = "disabled";
 };
 
+&hynitron {
+	status = "disabled";
+};
+
 &i2c4 {
 	clock-frequency = <400000>;
 	status = "okay";

arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x.dtsi

@@ -152,6 +152,25 @@
 		goodix,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>;
 		power-supply = <&vcc3v3_lcd_n>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc3v3_lcd_n>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2c8 {
@@ -253,6 +272,22 @@
 				<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
 				<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb-typec {

arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi

@@ -494,6 +494,25 @@
 		goodix,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>;
 		power-supply = <&vcc3v3_lcd_n>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc3v3_lcd_n>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &i2c5 {
@@ -688,6 +707,22 @@
 				<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
 				<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rk3588s.dtsi

@@ -2509,7 +2509,6 @@
 	rkcif_dvp: rkcif-dvp {
 		compatible = "rockchip,rkcif-dvp";
 		rockchip,hw = <&rkcif>;
-		iommus = <&rkcif_mmu>;
 		status = "disabled";
 	};
 
@@ -2522,7 +2521,6 @@
 	rkcif_mipi_lvds: rkcif-mipi-lvds {
 		compatible = "rockchip,rkcif-mipi-lvds";
 		rockchip,hw = <&rkcif>;
-		iommus = <&rkcif_mmu>;
 		status = "disabled";
 	};
 
@@ -2553,7 +2551,6 @@
 	rkcif_mipi_lvds1: rkcif-mipi-lvds1 {
 		compatible = "rockchip,rkcif-mipi-lvds";
 		rockchip,hw = <&rkcif>;
-		iommus = <&rkcif_mmu>;
 		status = "disabled";
 	};
 
@@ -2584,7 +2581,6 @@
 	rkcif_mipi_lvds2: rkcif-mipi-lvds2 {
 		compatible = "rockchip,rkcif-mipi-lvds";
 		rockchip,hw = <&rkcif>;
-		iommus = <&rkcif_mmu>;
 		status = "disabled";
 	};
 
@@ -2615,7 +2611,6 @@
 	rkcif_mipi_lvds3: rkcif-mipi-lvds3 {
 		compatible = "rockchip,rkcif-mipi-lvds";
 		rockchip,hw = <&rkcif>;
-		iommus = <&rkcif_mmu>;
 		status = "disabled";
 	};
 
@@ -2646,7 +2641,6 @@
 	rkcif_mipi_lvds4: rkcif-mipi-lvds4 {
 		compatible = "rockchip,rkcif-mipi-lvds";
 		rockchip,hw = <&rkcif>;
-		iommus = <&rkcif_mmu>;
 		status = "disabled";
 	};
 
@@ -2677,7 +2671,6 @@
 	rkcif_mipi_lvds5: rkcif-mipi-lvds5 {
 		compatible = "rockchip,rkcif-mipi-lvds";
 		rockchip,hw = <&rkcif>;
-		iommus = <&rkcif_mmu>;
 		status = "disabled";
 	};
 

arch/arm64/boot/dts/rockchip/rv1126b-evb-dual-cam-4k.dtsi

@@ -25,6 +25,12 @@
 				remote-endpoint = <&imx415_out0>;
 				data-lanes = <1 2 3 4>;
 			};
+
+			csi_dphy_input1: endpoint@2 {
+				reg = <2>;
+				remote-endpoint = <&sc850sl_out0>;
+				data-lanes = <1 2 3 4>;
+			};
 		};
 		port@1 {
 			reg = <1>;
@@ -55,6 +61,13 @@
 				remote-endpoint = <&imx415_out1>;
 				data-lanes = <1 2 3 4>;
 			};
+
+			csi_dphy3_input1: endpoint@2 {
+				reg = <2>;
+				remote-endpoint = <&sc850sl_out1>;
+				data-lanes = <1 2 3 4>;
+			};
+
 		};
 		port@1 {
 			reg = <1>;
@@ -112,6 +125,55 @@
 			};
 		};
 	};
+
+	sc850sl_0: sc850sl_0@30 {
+		compatible = "smartsens,sc850sl";
+		status = "okay";
+		reg = <0x30>;
+		clocks = <&cru CLK_MIPI0_OUT2IO>;
+		clock-names = "xvclk";
+		reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>;
+		pwdn-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cam_clk0_pins>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "default";
+		rockchip,camera-module-lens-name = "default";
+		port {
+			sc850sl_out0: endpoint {
+				remote-endpoint = <&csi_dphy_input1>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+};
+
+&i2c4 {
+	status = "okay";
+	pinctrl-0 = <&i2c4m3_pins>;
+
+	sc850sl_1: sc850sl_1@30 {
+		compatible = "smartsens,sc850sl";
+		status = "okay";
+		reg = <0x30>;
+		clocks = <&cru CLK_MIPI2_OUT2IO>;
+		clock-names = "xvclk";
+		reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>;
+		pwdn-gpios = <&gpio5 RK_PB0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cam_clk2_pins>;
+		rockchip,camera-module-index = <1>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "default";
+		rockchip,camera-module-lens-name = "default";
+		port {
+			sc850sl_out1: endpoint {
+				remote-endpoint = <&csi_dphy3_input1>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
 };
 
 &mipi0_csi2 {

arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10.dtsi

@@ -319,6 +319,25 @@
 		goodix,rst-gpio = <&gpio7 RK_PA7 GPIO_ACTIVE_HIGH>;
 		goodix,irq-gpio = <&gpio7 RK_PA6 IRQ_TYPE_LEVEL_LOW>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc_mipi>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio7 RK_PA7 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio7 RK_PA6 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &mdio {
@@ -368,6 +387,22 @@
 				<7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
 				<7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10-aov-dual-cam.dts

@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+#include "rv1126b.dtsi"
+#include "rv1126b-evb.dtsi"
+#include "rv1126b-evb2-v10.dtsi"
+#include "rv1126b-evb-dual-cam-4k.dtsi"
+
+/ {
+	model = "Rockchip RV1126B EVB2 V10 Board";
+	compatible = "rockchip,rv1126b-evb2-v10", "rockchip,rv1126b";
+};
+
+&rockchip_suspend {
+	status = "okay";
+
+	rockchip,sleep-pin-config = <
+		(0
+		| RKPM_SLEEP_PIN0_EN
+		)
+		(0
+		| RKPM_SLEEP_PIN0_ACT_LOW
+		)
+	>;
+
+	rockchip,sleep-io-config = <
+		/* pmic_sleep */
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(0)
+		)
+		/* reset */
+		#if 0
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_NONE
+		| RKPM_IO_CFG_ID(1)
+		)
+		#endif
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(2)
+		)
+		(0
+		| RKPM_IO_CFG_PULL_NONE
+		| RKPM_IO_CFG_ID(3)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_UP
+		| RKPM_IO_CFG_ID(4)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(5)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(6)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_UP
+		| RKPM_IO_CFG_ID(7)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(8)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(9)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(10)
+		)
+		/* uart0 tx */
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(11)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(12)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(16)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(17)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_NONE
+		| RKPM_IO_CFG_ID(18)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_NONE
+		| RKPM_IO_CFG_ID(19)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(20)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(21)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(22)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(23)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(24)
+		)
+		(0
+		| RKPM_IO_CFG_IOMUX_GPIO
+		| RKPM_IO_CFG_GPIO_DIR_INPUT
+		| RKPM_IO_CFG_PULL_DOWN
+		| RKPM_IO_CFG_ID(25)
+		)
+	>;
+};
+
+&sc850sl_0 {
+	reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+	rockchip,camera-module-stb = <1>;
+};
+
+&sc850sl_1 {
+	reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+	rockchip,camera-module-stb = <1>;
+};

arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dtsi

@@ -301,6 +301,25 @@
 		goodix,rst-gpio = <&gpio5 RK_PD6 GPIO_ACTIVE_HIGH>;
 		goodix,irq-gpio = <&gpio3 RK_PB7 IRQ_TYPE_LEVEL_LOW>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc_lcd>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio5 RK_PD6 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &mdio {
@@ -340,6 +359,22 @@
 				<3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
 				<5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rv1126b-evb3-v10.dts

@@ -324,6 +324,25 @@
 		goodix,rst-gpio = <&gpio5 RK_PD6 GPIO_ACTIVE_HIGH>;
 		goodix,irq-gpio = <&gpio3 RK_PB7 IRQ_TYPE_LEVEL_LOW>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc_mipi>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio5 RK_PD6 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &mipi2_csi2 {
@@ -485,6 +504,22 @@
 				<3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
 				<5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		ts_int_active: ts_int_active {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

arch/arm64/boot/dts/rockchip/rv1126b-evb4-v10.dts

@@ -362,6 +362,25 @@
 		goodix,rst-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
 		goodix,irq-gpio = <&gpio0 RK_PA7 IRQ_TYPE_LEVEL_LOW>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc_mipi>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &mdio {
@@ -405,6 +424,24 @@
 		};
 	};
 
+	touch {
+		ts_int_active: ts_int_active {
+			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
 	usb {
 		typec5v_pwren: typec5v-pwren {
 			rockchip,pins = <5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;

arch/arm64/boot/dts/rockchip/rv1126bp-evb-v14.dtsi

@@ -424,6 +424,25 @@
 		goodix,rst-gpio = <&gpio5 RK_PA4 GPIO_ACTIVE_HIGH>;
 		goodix,irq-gpio = <&gpio5 RK_PA6 IRQ_TYPE_LEVEL_LOW>;
 	};
+
+	hynitron: hynitron@5a {
+		compatible = "hyn,3240";
+		reg = <0x5a>;
+		power-supply = <&vcc_mipi>;
+
+		pinctrl-names = "ts_active","ts_suspend";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&gpio5 RK_PA4 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&gpio5 RK_PA6 GPIO_ACTIVE_LOW>;
+
+		max-touch-number = <5>;
+		display-coords = <0 0 1080 1920>;
+		pos-swap = <0>;
+		posx-reverse = <0>;
+		posy-reverse = <0>;
+	};
 };
 
 &mdio {
@@ -457,6 +476,24 @@
 		};
 	};
 
+	touch {
+		ts_int_active: ts_int_active {
+			rockchip,pins = <5 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_reset_active: ts_reset_active {
+			rockchip,pins = <5 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		ts_int_suspend: ts_int_suspend {
+			rockchip,pins = <5 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		ts_reset_suspend: ts_reset_suspend {
+			rockchip,pins = <5 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
 	wireless-bluetooth {
 		uart2_gpios: uart2-gpios {
 			rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;

arch/arm64/configs/rk3576_vehicle.config

@@ -173,6 +173,7 @@ CONFIG_VIDEO_MAXIM_CAM_DUMMY=y
 # CONFIG_VIDEO_MAXIM_CAM_OS04A10 is not set
 CONFIG_VIDEO_MAXIM_CAM_OV231X=y
 CONFIG_VIDEO_MAXIM_CAM_OX01F10=y
+CONFIG_VIDEO_MAXIM_CAM_OX03C10=y
 CONFIG_VIDEO_MAXIM_CAM_OX03J10=y
 CONFIG_VIDEO_MAXIM_CAM_SC320AT=y
 # CONFIG_VIDEO_MAXIM_DES_MAXIM2C is not set

arch/arm64/configs/rk3588_vehicle.config

@@ -48,6 +48,7 @@ CONFIG_MALI_VALHALL=y
 # CONFIG_MFD_RKX110_X120 is not set
 CONFIG_MFD_SERDES_DISPLAY=y
 # CONFIG_PROXIMITY_DEVICE is not set
+CONFIG_PWM_R7F701=y
 # CONFIG_R8168 is not set
 CONFIG_REALTEK_PHY=y
 # CONFIG_REGULATOR_ACT8865 is not set
@@ -120,7 +121,6 @@ CONFIG_VIDEO_MAXIM_SERDES=y
 # CONFIG_VIDEO_SGM3784 is not set
 # CONFIG_VL6180 is not set
 CONFIG_MALI_CSF_INCLUDE_FW=y
-# CONFIG_MALI_VALHALL_ARBITRATION is not set
 # CONFIG_MALI_VALHALL_CORESIGHT is not set
 # CONFIG_MALI_VALHALL_CORESTACK is not set
 CONFIG_MALI_VALHALL_CSF_SUPPORT=y
@@ -146,6 +146,7 @@ CONFIG_MALI_VALHALL_TRACE_POWER_GPU_WORK_PERIOD=y
 # CONFIG_ROCKCHIP_DRM_SELF_TEST is not set
 CONFIG_SERDES_DISPLAY_CHIP_MAXIM=y
 CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96745=y
+CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96749=y
 CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96752=y
 CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96755=y
 CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96772=y

arch/arm64/configs/rockchip_linux_defconfig

@@ -237,6 +237,7 @@ CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ATMEL_MXT=y
 CONFIG_TOUCHSCREEN_GSL3673=y
 CONFIG_TOUCHSCREEN_GT1X=y
+CONFIG_TOUCHSCREEN_HYN=y
 CONFIG_TOUCHSCREEN_ELAN=y
 CONFIG_TOUCHSCREEN_USB_COMPOSITE=y
 CONFIG_ROCKCHIP_REMOTECTL=y

drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c

@@ -281,6 +281,9 @@ struct dw_mipi_dsi2 {
 
 	struct gpio_desc *te_gpio;
 
+	/* rockchip,split-mode */
+	bool split_mode;
+
 	/* split with other display interface */
 	bool dual_connector_split;
 	bool left_display;
@@ -1211,14 +1214,27 @@ dw_mipi_dsi2_encoder_helper_funcs = {
 static int dw_mipi_dsi2_connector_get_modes(struct drm_connector *connector)
 {
 	struct dw_mipi_dsi2 *dsi2 = con_to_dsi2(connector);
+	struct drm_display_info *di = &connector->display_info;
+	int num_modes = 0;
 
 	if (dsi2->bridge && (dsi2->bridge->ops & DRM_BRIDGE_OP_MODES))
-		return drm_bridge_get_modes(dsi2->bridge, connector);
+		num_modes = drm_bridge_get_modes(dsi2->bridge, connector);
 
 	if (dsi2->panel)
-		return drm_panel_get_modes(dsi2->panel, connector);
+		num_modes = drm_panel_get_modes(dsi2->panel, connector);
 
-	return -EINVAL;
+	if (!num_modes)
+		return -EINVAL;
+
+	if (dsi2->split_mode && dsi2->slave) {
+		struct drm_display_mode *mode;
+
+		di->width_mm *= 2;
+		list_for_each_entry(mode, &connector->probed_modes, head)
+			drm_mode_convert_to_split_mode(mode);
+	}
+
+	return num_modes;
 }
 
 static enum drm_mode_status
@@ -1382,7 +1398,8 @@ static struct dw_mipi_dsi2 *dw_mipi_dsi2_find_by_id(struct device_driver *drv,
 
 static int dw_mipi_dsi2_dual_channel_probe(struct dw_mipi_dsi2 *dsi2)
 {
-	if (of_property_read_bool(dsi2->dev->of_node, "rockchip,dual-channel")) {
+	if (of_property_read_bool(dsi2->dev->of_node, "rockchip,dual-channel") ||
+	    of_property_read_bool(dsi2->dev->of_node, "rockchip,split-mode")) {
 		dsi2->data_swap = of_property_read_bool(dsi2->dev->of_node,
 							"rockchip,data-swap");
 
@@ -1390,8 +1407,13 @@ static int dw_mipi_dsi2_dual_channel_probe(struct dw_mipi_dsi2 *dsi2)
 		if (!dsi2->slave)
 			return -EPROBE_DEFER;
 
+		if (of_property_read_bool(dsi2->dev->of_node, "rockchip,split-mode"))
+			dsi2->split_mode = true;
+
 		dsi2->slave->master = dsi2;
-		dsi2->lanes /= 2;
+
+		if (!dsi2->split_mode)
+			dsi2->lanes /= 2;
 
 		dsi2->slave->auto_calc_mode = dsi2->auto_calc_mode;
 		dsi2->slave->lanes = dsi2->lanes;
@@ -1491,7 +1513,7 @@ static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2,
 
 	dsi2->pps = pps;
 
-	if (dsi2->slave) {
+	if (dsi2->slave && !dsi2->split_mode) {
 		u16 pic_width = be16_to_cpu(pps->pic_width) / 2;
 
 		dsi2->pps->pic_width = cpu_to_be16(pic_width);

drivers/gpu/drm/rockchip/rockchip_drm_vop.h

@@ -914,6 +914,7 @@ struct vop2_win_regs {
 
 struct vop2_video_port_regs {
 	struct vop_reg cfg_done;
+	struct vop_reg sys_cfg_done;
 	struct vop_reg overlay_mode;
 	struct vop_reg dsp_background;
 	struct vop_reg port_mux;
@@ -1234,6 +1235,7 @@ struct vop2_win_data {
 	uint8_t axi_uv_id;
 	uint8_t possible_vp_mask;
 	uint8_t dci_rid_id;
+	uint8_t reg_done_bit;
 
 	uint32_t base;
 	enum drm_plane_type type;
@@ -1464,6 +1466,7 @@ struct vop_data {
 struct vop2_ctrl {
 	struct vop_reg cfg_done_en;
 	struct vop_reg wb_cfg_done;
+	struct vop_reg win_cfg_done;
 	struct vop_reg auto_gating_en;
 	struct vop_reg aclk_pre_auto_gating_en;
 	struct vop_reg dma_finish_mode;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

@@ -458,6 +458,7 @@ struct vop2_win {
 	uint8_t axi_uv_id;
 	uint8_t scale_engine_num;
 	uint8_t possible_vp_mask;
+	uint8_t reg_done_bit;
 	enum drm_plane_type type;
 	unsigned int max_upscale_factor;
 	unsigned int max_downscale_factor;
@@ -781,6 +782,11 @@ struct vop2_video_port {
 	 * @plane_mask_prop: plane mask interaction with userspace
 	 */
 	struct drm_property *plane_mask_prop;
+	/**
+	 * @reserved_plane_mask_prop: reserved plane mask interaction with userspace
+	 */
+	struct drm_property *reserved_plane_mask_prop;
+
 	/**
 	 * @feature_prop: crtc feature interaction with userspace
 	 */
@@ -835,6 +841,12 @@ struct vop2_video_port {
 	 */
 	int primary_plane_phy_id;
 
+	/**
+	 * @reserved_plane_phy_id: reserved plane is used by third party OS,
+	 * reserved plane is always on the top of overlay.
+	 */
+	int reserved_plane_phy_id;
+
 	struct post_acm acm_info;
 	struct post_csc csc_info;
 
@@ -872,6 +884,11 @@ struct vop2_video_port {
 	 * we configure whether sharp is disabled in dts
 	 */
 	bool sharp_disabled;
+
+	/**
+	 * @win_cfg_done_bits: control reg done bit for each win
+	 */
+	u32 win_cfg_done_bits;
 };
 
 struct vop2_extend_pll {
@@ -956,6 +973,7 @@ struct vop2 {
 	unsigned long aclk_current_freq;
 	enum rockchip_drm_vop_aclk_mode aclk_mode;
 	bool merge_irq;
+	bool enable_reserved_plane;
 
 	const struct vop2_data *data;
 	/* Number of win that registered as plane,
@@ -1929,8 +1947,15 @@ static inline void rk3588_vop2_cfg_done(struct drm_crtc *crtc)
 		val |= BIT(vp_data->splice_vp_id) | (BIT(vp_data->splice_vp_id) << 16);
 
 	rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val);
+	if (vp->reserved_plane_phy_id != ROCKCHIP_VOP2_PHY_ID_INVALID) {
+		val = vp->win_cfg_done_bits;
+		VOP_CTRL_SET(vop2, win_cfg_done, val);
+		VOP_CTRL_SET(vop2, wb_cfg_done, 1);
+		VOP_MODULE_SET(vop2, vp, sys_cfg_done, 1);
+	} else {
+		vop2_writel(vop2, 0, val);
+	}
 
-	vop2_writel(vop2, 0, val);
 }
 
 static inline void vop2_wb_cfg_done(struct vop2_video_port *vp)
@@ -2201,6 +2226,8 @@ static void vop2_win_multi_area_disable(struct vop2_win *parent)
 static void vop2_win_disable(struct vop2_win *win, bool skip_splice_win)
 {
 	struct vop2 *vop2 = win->vop2;
+	struct vop2_video_port *vp = NULL;
+	uint32_t vp_id;
 
 	/* Disable the right splice win */
 	if (win->splice_win && !skip_splice_win) {
@@ -2257,6 +2284,15 @@ static void vop2_win_disable(struct vop2_win *win, bool skip_splice_win)
 				win->pd->vp_mask &= ~win->vp_mask;
 			}
 		}
+
+		vp_id = ffs(win->vp_mask) - 1;
+		if (vp_id >= ROCKCHIP_MAX_CRTC) {
+			DRM_ERROR("Unsupported vp_id: %d\n", vp_id);
+			return;
+		}
+		vp = &vop2->vps[vp_id];
+		if (vp->reserved_plane_phy_id != ROCKCHIP_VOP2_PHY_ID_INVALID)
+			vp->win_cfg_done_bits |= BIT(win->reg_done_bit);
 	}
 
 	if (win->left_win && win->splice_mode_right) {
@@ -4676,8 +4712,14 @@ static void vop2_initial(struct drm_crtc *crtc)
 			vop2_mask_write(vop2, 0x700, 0x3, 4, 0, 0, true);
 
 		if (vop2->version == VOP_VERSION_RK3576) {
-			/* Default use rkiommu 2.0 for axi0 */
-			VOP_CTRL_SET(vop2, rkmmu_v2_en, 1);
+			/* reserved plane mode will enable iommu bypass for rtos reserved plane display,
+			 * but rkiommu 2.0 can't support iommu bypass function, so use rkiommu 1.0
+			 * at reserved plane mode by default, others will use rkiommu 2.0 by default.
+			 */
+			if (vop2->enable_reserved_plane)
+				VOP_CTRL_SET(vop2, rkmmu_v2_en, 0);
+			else /* Default use rkiommu 2.0 for axi0 */
+				VOP_CTRL_SET(vop2, rkmmu_v2_en, 1);
 
 			if (vop2->merge_irq == true)
 				VOP_CTRL_SET(vop2, vp_intr_merge_en, 1);
@@ -7122,6 +7164,7 @@ static void vop2_win_atomic_update(struct vop2_win *win, struct drm_rect *src, s
 		VOP_CLUSTER_SET(vop2, win, frm_reset_en, 1);
 		VOP_CLUSTER_SET(vop2, win, dma_stride_4k_disable, 1);
 	}
+	vp->win_cfg_done_bits |= BIT(win->reg_done_bit);
 	spin_unlock(&vop2->reg_lock);
 }
 
@@ -12142,10 +12185,18 @@ static void vop3_setup_layer_sel_for_vp(struct vop2_video_port *vp,
 	struct vop2_win *win;
 	u32 layer_sel = 0;
 	u8 layer_sel_id;
-	u8 layer_sel_none = 0xff;
+	u8 layer_sel_none = 0xf;
 	int i;
+	int nr_layers = vop2->data->nr_layers;
 
-	for (i = 0; i < vop2->data->nr_layers; i++) {
+	if (vp->reserved_plane_phy_id != ROCKCHIP_VOP2_PHY_ID_INVALID) {
+		/* set reserved layer at the top layer */
+		nr_layers -= 1;
+		win = vop2_find_win_by_phys_id(vop2, vp->reserved_plane_phy_id);
+		layer_sel = win->layer_sel_id[vp->id] << nr_layers * 4;
+	}
+
+	for (i = 0; i < nr_layers; i++) {
 		layer_sel_id = layer_sel_none;
 		if (i < vp->nr_layers) {
 			zpos = &vop2_zpos[i];
@@ -13476,6 +13527,7 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_stat
 	spin_lock_irqsave(&vop2->irq_lock, flags);
 	vop2_wb_commit(crtc);
 	vop2_cfg_done(crtc);
+	vp->win_cfg_done_bits = 0;
 
 	if (vp->mcu_timing.mcu_pix_total)
 		VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 0);
@@ -13764,6 +13816,11 @@ static int vop2_crtc_atomic_get_property(struct drm_crtc *crtc,
 		return 0;
 	}
 
+	if (property == vp->reserved_plane_mask_prop) {
+		*val = BIT(vp->reserved_plane_phy_id);
+		return 0;
+	}
+
 	if (property == vp->hdr_ext_data_prop) {
 		*val = vcstate->hdr_ext_data ? vcstate->hdr_ext_data->base.id : 0;
 		return 0;
@@ -13805,6 +13862,7 @@ static int vop2_crtc_atomic_set_property(struct drm_crtc *crtc,
 	struct drm_mode_config *mode_config = &drm_dev->mode_config;
 	struct vop2_video_port *vp = to_vop2_video_port(crtc);
 	struct vop2 *vop2 = vp->vop2;
+	const struct vop2_data *vop2_data = vop2->data;
 	bool replaced = false;
 	int ret;
 
@@ -13894,6 +13952,14 @@ static int vop2_crtc_atomic_set_property(struct drm_crtc *crtc,
 		return 0;
 	}
 
+	if (property == vp->reserved_plane_mask_prop) {
+		if (!val || hweight32(val) > 1 || !(val & vop2_data->plane_mask_base))
+			vp->reserved_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID;
+		else
+			vp->reserved_plane_phy_id = ilog2(val);
+		return 0;
+	}
+
 	if (property == vp->hdr_ext_data_prop) {
 		ret = vop2_atomic_replace_property_blob_from_id(drm_dev,
 								&vcstate->hdr_ext_data,
@@ -14798,6 +14864,38 @@ static int vop2_gamma_init(struct vop2 *vop2)
 	return 0;
 }
 
+static int vop2_crtc_create_reserved_plane_mask_property(struct vop2 *vop2,
+							 struct drm_crtc *crtc)
+{
+	struct drm_property *prop;
+	struct vop2_video_port *vp = to_vop2_video_port(crtc);
+
+	static const struct drm_prop_enum_list props[] = {
+		{ ROCKCHIP_VOP2_CLUSTER0, "Cluster0" },
+		{ ROCKCHIP_VOP2_CLUSTER1, "Cluster1" },
+		{ ROCKCHIP_VOP2_ESMART0, "Esmart0" },
+		{ ROCKCHIP_VOP2_ESMART1, "Esmart1" },
+		{ ROCKCHIP_VOP2_SMART0, "Smart0" },
+		{ ROCKCHIP_VOP2_SMART1, "Smart1" },
+		{ ROCKCHIP_VOP2_CLUSTER2, "Cluster2" },
+		{ ROCKCHIP_VOP2_CLUSTER3, "Cluster3" },
+		{ ROCKCHIP_VOP2_ESMART2, "Esmart2" },
+		{ ROCKCHIP_VOP2_ESMART3, "Esmart3" },
+	};
+
+	prop = drm_property_create_bitmask(vop2->drm_dev, 0, "RESERVED_PLANE_MASK",
+					   props, ARRAY_SIZE(props), 0xffffffff);
+	if (!prop) {
+		DRM_DEV_ERROR(vop2->dev, "create reserved_plane_mask prop for vp%d failed\n", vp->id);
+		return -ENOMEM;
+	}
+
+	vp->reserved_plane_mask_prop = prop;
+	drm_object_attach_property(&crtc->base, vp->reserved_plane_mask_prop, BIT(vp->reserved_plane_phy_id));
+
+	return 0;
+}
+
 static int vop2_crtc_create_plane_mask_property(struct vop2 *vop2,
 						struct drm_crtc *crtc,
 						uint32_t plane_mask)
@@ -15246,6 +15344,10 @@ static int vop2_create_crtc(struct vop2 *vop2, uint8_t enabled_vp_mask)
 		 */
 		if (plane_mask && !is_vop3(vop2))
 			vop2_crtc_create_plane_mask_property(vop2, crtc, plane_mask);
+
+		if (vp->reserved_plane_phy_id != ROCKCHIP_VOP2_PHY_ID_INVALID)
+			vop2_crtc_create_reserved_plane_mask_property(vop2, crtc);
+
 		vop2_crtc_create_feature_property(vop2, crtc);
 		vop2_crtc_create_vrr_property(vop2, crtc);
 
@@ -15477,6 +15579,7 @@ static int vop2_win_init(struct vop2 *vop2)
 		win->axi_yrgb_id = win_data->axi_yrgb_id;
 		win->axi_uv_id = win_data->axi_uv_id;
 		win->possible_vp_mask = win_data->possible_vp_mask;
+		win->reg_done_bit = win_data->reg_done_bit;
 
 		if (win_data->pd_id)
 			win->pd = vop2_find_pd_by_id(vop2, win_data->pd_id);
@@ -16316,6 +16419,7 @@ static int vop2_bind(struct device *dev, struct device *master, void *data)
 		for_each_child_of_node(vop_out_node, child) {
 			u32 plane_mask = 0;
 			u32 primary_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID;
+			u32 reserved_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID;
 			u32 vp_id = 0;
 			u32 val = 0;
 
@@ -16330,7 +16434,12 @@ static int vop2_bind(struct device *dev, struct device *master, void *data)
 				vop2->vps[vp_id].primary_plane_phy_id = primary_plane_phy_id;
 			else
 				vop2->vps[vp_id].primary_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID;
-
+			if (!of_property_read_u32(child, "rockchip,reserved-plane", &reserved_plane_phy_id)) {
+				vop2->vps[vp_id].reserved_plane_phy_id = reserved_plane_phy_id;
+				vop2->enable_reserved_plane = true;
+			} else {
+				vop2->vps[vp_id].reserved_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID;
+			}
 			vop2->vps[vp_id].xmirror_en = of_property_read_bool(child, "xmirror-enable");
 
 			ret = of_clk_set_defaults(child, false);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

@@ -1022,7 +1022,8 @@ static const struct vop2_wb_data rk3576_vop_wb_data = {
 };
 
 static const struct vop2_video_port_regs rk3528_vop_vp0_regs = {
-	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
+	.cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 0),
+	.sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 4),
 	.overlay_mode = VOP_REG(RK3528_OVL_PORT0_CTRL, 0x1, 0),
 	.dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0),
 	.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
@@ -1100,7 +1101,8 @@ static const struct vop2_video_port_regs rk3528_vop_vp0_regs = {
 };
 
 static const struct vop2_video_port_regs rk3528_vop_vp1_regs = {
-	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1),
+	.cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 1),
+	.sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 5),
 	.overlay_mode = VOP_REG(RK3528_OVL_PORT1_CTRL, 0x1, 0),
 	.dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0xffffffff, 0),
 	.out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
@@ -1236,7 +1238,8 @@ static const struct vop2_video_port_data rk3528_vop_video_ports[] = {
 };
 
 static const struct vop2_video_port_regs rk3562_vop_vp0_regs = {
-	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
+	.cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 0),
+	.sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 4),
 	.overlay_mode = VOP_REG(RK3528_OVL_PORT0_CTRL, 0x1, 0),
 	.dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0),
 	.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
@@ -1326,6 +1329,7 @@ static const struct vop2_video_port_data rk3562_vop_video_ports[] = {
 
 static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
 	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
+	.sys_cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 4),
 	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0),
 	.dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0x3fffffff, 0),
 	.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 0),
@@ -1413,6 +1417,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
 
 static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
 	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1),
+	.sys_cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 5),
 	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 1),
 	.dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0x3fffffff, 0),
 	.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 4),
@@ -1467,6 +1472,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
 
 static const struct vop2_video_port_regs rk3568_vop_vp2_regs = {
 	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 2),
+	.sys_cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 6),
 	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 2),
 	.dsp_background = VOP_REG(RK3568_VP2_DSP_BG, 0x3fffffff, 0),
 	.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 8),
@@ -1559,7 +1565,8 @@ static const struct vop2_video_port_data rk3568_vop_video_ports[] = {
 };
 
 static const struct vop2_video_port_regs rk3576_vop_vp0_regs = {
-	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
+	.cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 0),
+	.sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 4),
 	.overlay_mode = VOP_REG(RK3528_OVL_PORT0_CTRL, 0x1, 0),
 	.dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0),
 	.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
@@ -1678,7 +1685,8 @@ static const struct vop2_video_port_regs rk3576_vop_vp0_regs = {
 };
 
 static const struct vop2_video_port_regs rk3576_vop_vp1_regs = {
-	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1),
+	.cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 1),
+	.sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 5),
 	.overlay_mode = VOP_REG(RK3528_OVL_PORT1_CTRL, 0x1, 0),
 	.dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0xffffffff, 0),
 	.out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
@@ -1769,7 +1777,8 @@ static const struct vop2_video_port_regs rk3576_vop_vp1_regs = {
 };
 
 static const struct vop2_video_port_regs rk3576_vop_vp2_regs = {
-	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 2),
+	.cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 2),
+	.sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 6),
 	.overlay_mode = VOP_REG(RK3576_OVL_PORT2_CTRL, 0x1, 0),
 	.dsp_background = VOP_REG(RK3568_VP2_DSP_BG, 0xffffffff, 0),
 	.out_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0xf, 0),
@@ -1935,7 +1944,8 @@ static const struct vop2_video_port_data rk3576_vop_video_ports[] = {
 };
 
 static const struct vop2_video_port_regs rk3588_vop_vp0_regs = {
-	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
+	.cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 0),
+	.sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 4),
 	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0),
 	.dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0),
 	.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 0),
@@ -2040,7 +2050,8 @@ static const struct vop2_video_port_regs rk3588_vop_vp0_regs = {
  * same eotf curve with VP1.
  */
 static const struct vop2_video_port_regs rk3588_vop_vp1_regs = {
-	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1),
+	.cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 1),
+	.sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 5),
 	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 1),
 	.dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0xffffffff, 0),
 	.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 4),
@@ -2132,7 +2143,8 @@ static const struct vop2_video_port_regs rk3588_vop_vp1_regs = {
 };
 
 static const struct vop2_video_port_regs rk3588_vop_vp2_regs = {
-	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 2),
+	.cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 2),
+	.sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 6),
 	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 2),
 	.dsp_background = VOP_REG(RK3568_VP2_DSP_BG, 0xffffffff, 0),
 	.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 8),
@@ -2195,7 +2207,8 @@ static const struct vop2_video_port_regs rk3588_vop_vp2_regs = {
 };
 
 static const struct vop2_video_port_regs rk3588_vop_vp3_regs = {
-	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 3),
+	.cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 3),
+	.sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 7),
 	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 3),
 	.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 12),
 	.dsp_background = VOP_REG(RK3588_VP3_DSP_BG, 0xffffffff, 0),
@@ -3143,6 +3156,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = {
 	  .axi_yrgb_id = 0x06,
 	  .axi_uv_id = 0x07,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0),
+	  .reg_done_bit = 4,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .dly = { 27, 45, 48 },
@@ -3172,6 +3186,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = {
 	  .axi_yrgb_id = 0x08,
 	  .axi_uv_id = 0x09,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0),
+	  .reg_done_bit = 5,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .dly = { 27, 45, 48 },
@@ -3201,6 +3216,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = {
 	  .axi_yrgb_id = 0x0a,
 	  .axi_uv_id = 0x0b,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1),
+	  .reg_done_bit = 6,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .dly = { 27, 45, 48 },
@@ -3230,6 +3246,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = {
 	  .axi_yrgb_id = 0x0c,
 	  .axi_uv_id = 0x0d,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP1),
+	  .reg_done_bit = 7,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .dly = { 27, 45, 48 },
@@ -3256,6 +3273,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = {
 	  .axi_yrgb_id = 0x02,
 	  .axi_uv_id = 0x03,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0),
+	  .reg_done_bit = 0,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .dly = { 27, 27, 21 },
@@ -3282,6 +3300,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = {
 	  .axi_yrgb_id = 0x04,
 	  .axi_uv_id = 0x05,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0),
+	  .reg_done_bit = 0,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .type = DRM_PLANE_TYPE_OVERLAY,
@@ -3325,6 +3344,7 @@ static const struct vop2_win_data rk3562_vop_win_data[] = {
 	  .axi_yrgb_id = 0x02,
 	  .axi_uv_id = 0x03,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0),
+	  .reg_done_bit = 4,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .dly = { 27, 45, 48 },
@@ -3352,6 +3372,7 @@ static const struct vop2_win_data rk3562_vop_win_data[] = {
 	  .axi_yrgb_id = 0x04,
 	  .axi_uv_id = 0x05,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0),
+	  .reg_done_bit = 5,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .dly = { 27, 45, 48 },
@@ -3379,6 +3400,7 @@ static const struct vop2_win_data rk3562_vop_win_data[] = {
 	  .axi_yrgb_id = 0x06,
 	  .axi_uv_id = 0x07,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0),
+	  .reg_done_bit = 6,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .dly = { 27, 45, 48 },
@@ -3406,6 +3428,7 @@ static const struct vop2_win_data rk3562_vop_win_data[] = {
 	  .axi_yrgb_id = 0x08,
 	  .axi_uv_id = 0x0d,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0),
+	  .reg_done_bit = 7,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .dly = { 27, 45, 48 },
@@ -3801,6 +3824,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = {
 	  .axi_yrgb_id = 0x10,
 	  .axi_uv_id = 0x11,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP2),
+	  .reg_done_bit = 4,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .feature = WIN_FEATURE_MULTI_AREA | WIN_FEATURE_Y2R_13BIT_DEPTH,
@@ -3830,6 +3854,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = {
 	  .axi_yrgb_id = 0x12,
 	  .axi_uv_id = 0x13,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2),
+	  .reg_done_bit = 5,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .feature = WIN_FEATURE_MULTI_AREA,
@@ -3859,6 +3884,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = {
 	  .axi_yrgb_id = 0x0a,
 	  .axi_uv_id = 0x0b,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP2),
+	  .reg_done_bit = 6,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .feature = WIN_FEATURE_MULTI_AREA,
@@ -3888,6 +3914,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = {
 	  .axi_yrgb_id = 0x0c,
 	  .axi_uv_id = 0x0d,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2),
+	  .reg_done_bit = 7,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .feature = WIN_FEATURE_MULTI_AREA,
@@ -3914,6 +3941,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = {
 	  .axi_uv_id = 0x0b,
 	  .dci_rid_id = 0x4,/* dci axi id length is 4 bits */
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1),
+	  .reg_done_bit = 0,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .type = DRM_PLANE_TYPE_OVERLAY,
@@ -3940,6 +3968,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = {
 	  .axi_yrgb_id = 0x0c,
 	  .axi_uv_id = 0x0d,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1),
+	  .reg_done_bit = 0,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .type = DRM_PLANE_TYPE_OVERLAY,
@@ -3966,6 +3995,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = {
 	  .axi_yrgb_id = 0x06,
 	  .axi_uv_id = 0x07,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1),/* vp0 or vp1 */
+	  .reg_done_bit = 1,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .type = DRM_PLANE_TYPE_OVERLAY,
@@ -3991,6 +4021,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = {
 	  .axi_yrgb_id = 0x08,
 	  .axi_uv_id = 0x09,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1),/* vp0 or vp1 */
+	  .reg_done_bit = 1,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .type = DRM_PLANE_TYPE_OVERLAY,
@@ -4288,6 +4319,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
 	  .axi_uv_id = 3,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) |
 			      BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3),
+	  .reg_done_bit = 0,
 	  .max_upscale_factor = 4,
 	  .max_downscale_factor = 4,
 	  .dly = { 4, 26, 29, 4, 35, 3, 5 },
@@ -4314,6 +4346,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
 	  .axi_uv_id = 5,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) |
 			      BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3),
+	  .reg_done_bit = 0,
 	  .max_upscale_factor = 4,
 	  .max_downscale_factor = 4,
 	  .type = DRM_PLANE_TYPE_OVERLAY,
@@ -4342,6 +4375,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
 	  .type = DRM_PLANE_TYPE_OVERLAY,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) |
 			      BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3),
+	  .reg_done_bit = 1,
 	  .max_upscale_factor = 4,
 	  .max_downscale_factor = 4,
 	  .dly = { 4, 26, 29, 4, 35, 3, 5 },
@@ -4368,6 +4402,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
 	  .axi_uv_id = 9,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) |
 			      BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3),
+	  .reg_done_bit = 1,
 	  .max_upscale_factor = 4,
 	  .max_downscale_factor = 4,
 	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
@@ -4396,6 +4431,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
 	  .axi_uv_id = 3,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) |
 			      BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3),
+	  .reg_done_bit = 2,
 	  .max_upscale_factor = 4,
 	  .max_downscale_factor = 4,
 	  .dly = { 4, 26, 29, 4, 35, 3, 5 },
@@ -4422,6 +4458,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
 	  .axi_uv_id = 5,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) |
 			      BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3),
+	  .reg_done_bit = 2,
 	  .max_upscale_factor = 4,
 	  .max_downscale_factor = 4,
 	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
@@ -4449,6 +4486,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
 	  .axi_uv_id = 7,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) |
 			      BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3),
+	  .reg_done_bit = 3,
 	  .max_upscale_factor = 4,
 	  .max_downscale_factor = 4,
 	  .dly = { 4, 26, 29, 4, 35, 3, 5 },
@@ -4475,6 +4513,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
 	  .axi_uv_id = 9,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) |
 			      BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3),
+	  .reg_done_bit = 3,
 	  .max_upscale_factor = 4,
 	  .max_downscale_factor = 4,
 	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
@@ -4503,6 +4542,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
 	  .axi_uv_id = 0x0b,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) |
 			      BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3),
+	  .reg_done_bit = 4,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .dly = { 23, 45, 48, 23, 54, 22, 24 },
@@ -4533,6 +4573,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
 	  .axi_uv_id = 0x0b,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) |
 			      BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3),
+	  .reg_done_bit = 6,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .dly = { 23, 45, 48, 23, 54, 22, 24 },
@@ -4562,6 +4603,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
 	  .axi_uv_id = 0x01,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) |
 			      BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3),
+	  .reg_done_bit = 5,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .dly = { 23, 45, 48, 23, 54, 22, 24 },
@@ -4591,6 +4633,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
 	  .axi_uv_id = 0x0d,
 	  .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) |
 			      BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3),
+	  .reg_done_bit = 7,
 	  .max_upscale_factor = 8,
 	  .max_downscale_factor = 8,
 	  .dly = { 23, 45, 48, 23, 54, 22, 24 },
@@ -4599,8 +4642,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
 };
 
 static const struct vop2_ctrl rk3528_vop_ctrl = {
-	.cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15),
+	.cfg_done_en = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 15),
 	.wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14),
+	.win_cfg_done = VOP_REG_MASK(RK3588_SYS_WIN_REG_CFG_DONE, 0xffffffff, 0),
 	.auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31),
 	.aclk_pre_auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 7),
 	.if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
@@ -4638,6 +4682,7 @@ static const struct vop_grf_ctrl rk3562_sys_grf_ctrl = {
 static const struct vop2_ctrl rk3562_vop_ctrl = {
 	.cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15),
 	.wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14),
+	.win_cfg_done = VOP_REG_MASK(RK3588_SYS_WIN_REG_CFG_DONE, 0xffffffff, 0),
 	.auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31),
 	.aclk_pre_auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 7),
 	.if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
@@ -4748,6 +4793,7 @@ static const struct vop2_ctrl rk3576_vop_ctrl = {
 	.cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15),
 	.reg_done_frm = VOP_REG_MASK(RK3576_SYS_PORT_CTRL_IMD, 0x7, 0),
 	.wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14),
+	.win_cfg_done = VOP_REG_MASK(RK3588_SYS_WIN_REG_CFG_DONE, 0xffffffff, 0),
 	.auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31),
 	.aclk_pre_auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 7),
 	.version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
@@ -4882,6 +4928,7 @@ static const struct vop_grf_ctrl rk3588_vo1_grf_ctrl = {
 static const struct vop2_ctrl rk3588_vop_ctrl = {
 	.cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15),
 	.wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14),
+	.win_cfg_done = VOP_REG_MASK(RK3588_SYS_WIN_REG_CFG_DONE, 0xffffffff, 0),
 	.auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31),
 	.dma_finish_mode = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x3, 0),
 	.axi_dma_finish_and_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 2),

drivers/gpu/drm/rockchip/rockchip_vop_reg.h

@@ -1064,6 +1064,7 @@
 #define RK3568_VOP2_GLB_CFG_DONE_EN		BIT(15)
 #define RK3568_VERSION_INFO			0x004
 #define RK3568_SYS_AUTO_GATING_CTRL		0x008
+#define RK3588_SYS_WIN_REG_CFG_DONE		0x00c
 #define RK3576_SYS_AXI_HURRY_CTRL0_IMD		0x014
 #define RK3576_SYS_AXI_HURRY_CTRL1_IMD		0x018
 #define RK3576_SYS_MMU_CTRL_IMD			0x020

drivers/media/i2c/maxim/remote/Kconfig

@@ -74,6 +74,15 @@ config VIDEO_MAXIM_CAM_OV231X
 	  To compile this driver as a module, choose M here: the
 	  module will be called ov231x.
 
+config VIDEO_MAXIM_CAM_OX03C10
+	tristate "Maxim Remote Sensor ox03c10 support"
+	depends on VIDEO_MAXIM_SERDES
+	help
+	  This driver supports the remote sensor ox03c10.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called ox03c10.
+
 config VIDEO_MAXIM_CAM_OX03J10
 	tristate "Maxim Remote Sensor ox03j10 support"
 	depends on VIDEO_MAXIM_SERDES

drivers/media/i2c/maxim/remote/Makefile

@@ -8,6 +8,7 @@ maxim-dummy-objs := dummy.o
 maxim-sc320at-objs := sc320at.o
 maxim-ox01f10-objs := ox01f10.o
 maxim-ov231x-objs := ov231x.o
+maxim-ox03c10-objs := ox03c10.o
 maxim-ox03j10-objs := ox03j10.o
 maxim-os04a10-objs := os04a10.o
 
@@ -15,5 +16,6 @@ obj-$(CONFIG_VIDEO_MAXIM_CAM_DUMMY)	+= maxim-dummy.o
 obj-$(CONFIG_VIDEO_MAXIM_CAM_SC320AT)	+= maxim-sc320at.o
 obj-$(CONFIG_VIDEO_MAXIM_CAM_OX01F10)	+= maxim-ox01f10.o
 obj-$(CONFIG_VIDEO_MAXIM_CAM_OV231X)	+= maxim-ov231x.o
+obj-$(CONFIG_VIDEO_MAXIM_CAM_OX03C10)	+= maxim-ox03c10.o
 obj-$(CONFIG_VIDEO_MAXIM_CAM_OX03J10)	+= maxim-ox03j10.o
 obj-$(CONFIG_VIDEO_MAXIM_CAM_OS04A10)	+= maxim-os04a10.o

drivers/media/i2c/os12d40.c

@@ -73,6 +73,16 @@
 #define	ANALOG_GAIN_DEFAULT		1024
 
 #define OS12D40_REG_GROUP		0x3208
+#define OS12D40_GROUP_UPDATE_START_DATA	0x00
+#define OS12D40_GROUP_UPDATE_END_DATA	0x10
+#define OS12D40_GROUP_UPDATE_LAUNCH		0xA0
+
+#define OS12D40_GROUP1_UPDATE_START_DATA	0x01
+#define OS12D40_GROUP1_UPDATE_END_DATA		0x11
+#define OS12D40_GROUP1_UPDATE_LAUNCH		0xA1
+
+#define OS12D40_REG_XOFFSET_L	0x3811
+#define OS12D40_REG_YOFFSET_L	0x3813
 #define OS12D40_REG_FLIP		0x3820
 #define OS12D40_REG_MIRROR		0x3821
 #define MIRROR_BIT_MASK			BIT(2)
@@ -1931,7 +1941,7 @@ static const struct regval os12d40_2256x1256_regs_4lane[] = {
 
 static const struct os12d40_mode supported_modes_4lane[] = {
 	{
-		.bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
+		.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
 		.width = 2256,
 		.height = 1256,
 		.max_fps = {
@@ -2774,6 +2784,7 @@ static int os12d40_set_ctrl(struct v4l2_ctrl *ctrl)
 	int ret = 0;
 	u32 again = 0;
 	u32 dgain = 0;
+	u32 offset = 0;
 
 	/* Propagate change of current control to all related controls */
 	switch (ctrl->id) {
@@ -2833,25 +2844,81 @@ static int os12d40_set_ctrl(struct v4l2_ctrl *ctrl)
 		ret = os12d40_read_reg(os12d40->client, OS12D40_REG_MIRROR,
 				       OS12D40_REG_VALUE_08BIT,
 				       &val);
-		if (ctrl->val)
-			val |= MIRROR_BIT_MASK;
-		else
+		if (ctrl->val) {
 			val &= ~MIRROR_BIT_MASK;
+			if (os12d40->cur_mode->width == 2256)
+				offset = 0x22;
+			else
+				offset = 0x40;
+		} else {
+			val |= MIRROR_BIT_MASK;
+			if (os12d40->cur_mode->width == 2256)
+				offset = 0x21;
+			else
+#if USE_4_CELL
+				offset = 0x3e;
+#else
+				offset = 0x3f;
+#endif
+		}
+		if (os12d40->streaming)
+			ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_GROUP,
+				OS12D40_REG_VALUE_08BIT,
+				OS12D40_GROUP_UPDATE_START_DATA);
+		ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_XOFFSET_L,
+				OS12D40_REG_VALUE_08BIT,
+				offset);
 		ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_MIRROR,
 					OS12D40_REG_VALUE_08BIT,
 					val);
+		if (os12d40->streaming) {
+			ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_GROUP,
+				OS12D40_REG_VALUE_08BIT,
+				OS12D40_GROUP_UPDATE_END_DATA);
+			ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_GROUP,
+				OS12D40_REG_VALUE_08BIT,
+				OS12D40_GROUP_UPDATE_LAUNCH);
+		}
 		break;
 	case V4L2_CID_VFLIP:
 		ret = os12d40_read_reg(os12d40->client, OS12D40_REG_FLIP,
 				       OS12D40_REG_VALUE_08BIT,
 				       &val);
-		if (ctrl->val)
+		if (ctrl->val) {
 			val |= FLIP_BIT_MASK;
-		else
+			if (os12d40->cur_mode->width == 2256)
+				offset = 0x05;
+			else
+#if USE_4_CELL
+				offset = 0x06;
+#else
+				offset = 0x07;
+#endif
+		} else {
 			val &= ~FLIP_BIT_MASK;
+			if (os12d40->cur_mode->width == 2256)
+				offset = 0x04;
+			else
+				offset = 0x08;
+		}
+		if (os12d40->streaming)
+			ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_GROUP,
+				OS12D40_REG_VALUE_08BIT,
+				OS12D40_GROUP1_UPDATE_START_DATA);
+		ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_YOFFSET_L,
+				OS12D40_REG_VALUE_08BIT,
+				offset);
 		ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_FLIP,
 					OS12D40_REG_VALUE_08BIT,
 					val);
+		if (os12d40->streaming) {
+			ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_GROUP,
+				OS12D40_REG_VALUE_08BIT,
+				OS12D40_GROUP1_UPDATE_END_DATA);
+			ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_GROUP,
+				OS12D40_REG_VALUE_08BIT,
+				OS12D40_GROUP1_UPDATE_LAUNCH);
+		}
 		break;
 	default:
 		dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",

drivers/media/i2c/sc132gs.c

@@ -50,24 +50,30 @@
 #define SC132GS_MODE_SW_STANDBY		0x0
 #define SC132GS_MODE_STREAMING		BIT(0)
 
-#define SC132GS_REG_EXPOSURE		0x3e01
-#define	SC132GS_EXPOSURE_MIN		6
+#define SC132GS_REG_EXPOSURE		0x3e00
+#define	SC132GS_EXPOSURE_MIN		1
 #define	SC132GS_EXPOSURE_STEP		1
 #define SC132GS_VTS_MAX			0xffff
 
 #define SC132GS_REG_COARSE_AGAIN	0x3e08
 #define SC132GS_REG_FINE_AGAIN		0x3e09
+#define SC132GS_REG_COARSE_DGAIN	0x3e06
+#define SC132GS_REG_FINE_DGAIN		0x3e07
+
 #define	ANALOG_GAIN_MIN			0x20
-#define	ANALOG_GAIN_MAX			0x391
+#define	ANALOG_GAIN_MAX			0x6c80
 #define	ANALOG_GAIN_STEP		1
 #define	ANALOG_GAIN_DEFAULT		0x20
 
 #define SC132GS_REG_TEST_PATTERN	0x4501
-#define	SC132GS_TEST_PATTERN_ENABLE	0xcc
-#define	SC132GS_TEST_PATTERN_DISABLE	0xc4
+#define SC132GS_TEST_PATTERN_BIT_MASK	BIT(3)
 
 #define SC132GS_REG_VTS			0x320e
 
+#define SC132GS_FLIP_REG		0x3221
+#define SC132GS_HFLIP_MASK		0x06
+#define SC132GS_VFLIP_MASK		0x60
+
 #define REG_NULL			0xFFFF
 
 #define SC132GS_REG_VALUE_08BIT		1
@@ -131,6 +137,8 @@ struct sc132gs {
 	struct v4l2_ctrl	*test_pattern;
 	struct v4l2_ctrl	*pixel_rate;
 	struct v4l2_ctrl	*link_freq;
+	struct v4l2_ctrl	*h_flip;
+	struct v4l2_ctrl	*v_flip;
 	struct mutex		mutex;
 	struct v4l2_fract	cur_fps;
 	u32			cur_vts;
@@ -141,6 +149,7 @@ struct sc132gs {
 	const char		*module_facing;
 	const char		*module_name;
 	const char		*len_name;
+	u8			flip;
 };
 
 #define to_sc132gs(sd) container_of(sd, struct sc132gs, subdev)
@@ -285,18 +294,18 @@ static const struct regval sc132gs_2lane_10bit_regs[] = {
 	{0x3018, 0x32},
 	{0x3019, 0x0c},
 	{0x301a, 0xb4},
-	{0x3031, 0x0a},
+	{0x301f, 0x51},
 	{0x3032, 0x60},
 	{0x3038, 0x44},
 	{0x3207, 0x17},
-	{0x320c, 0x05},
-	{0x320d, 0xdc},
-	{0x320e, 0x09},
-	{0x320f, 0x60},
+	{0x320c, 0x02},
+	{0x320d, 0xee},
+	{0x320e, 0x05},
+	{0x320f, 0x78},
 	{0x3250, 0xcc},
 	{0x3251, 0x02},
-	{0x3252, 0x09},
-	{0x3253, 0x5b},
+	{0x3252, 0x05},
+	{0x3253, 0x73},
 	{0x3254, 0x05},
 	{0x3255, 0x3b},
 	{0x3306, 0x78},
@@ -331,18 +340,22 @@ static const struct regval sc132gs_2lane_10bit_regs[] = {
 	{0x363b, 0x48},
 	{0x363c, 0x83},
 	{0x363d, 0x10},
-	{0x36ea, 0x38},
-	{0x36fa, 0x25},
-	{0x36fb, 0x05},
-	{0x36fd, 0x04},
+	{0x36ea, 0x36},
+	{0x36eb, 0x04},
+	{0x36ec, 0x13},
+	{0x36ed, 0x24},
+	{0x36fa, 0x2b},
+	{0x36fb, 0x1b},
+	{0x36fc, 0x11},
+	{0x36fd, 0x34},
 	{0x3900, 0x11},
 	{0x3901, 0x05},
 	{0x3902, 0xc5},
 	{0x3904, 0x04},
 	{0x3908, 0x91},
 	{0x391e, 0x00},
-	{0x3e01, 0x11},
-	{0x3e02, 0x20},
+	{0x3e01, 0x4e},
+	{0x3e02, 0xc0},
 	{0x3e09, 0x20},
 	{0x3e0e, 0xd2},
 	{0x3e14, 0xb0},
@@ -350,7 +363,7 @@ static const struct regval sc132gs_2lane_10bit_regs[] = {
 	{0x3e26, 0x20},
 	{0x4418, 0x38},
 	{0x4503, 0x10},
-	{0x4837, 0x21},
+	{0x4837, 0x35},
 	{0x5000, 0x0e},
 	{0x540c, 0x51},
 	{0x550f, 0x38},
@@ -374,15 +387,15 @@ static const struct regval sc132gs_2lane_10bit_regs[] = {
 	//flip
 	//{0x3221, (0x3 << 5)},
 
-	//mirror
-	{0x3221, (0x3 << 1)},
-
-	//flip & mirror
-	//{0x3221, ((0x3 << 1)|(0x3 << 5))},
 
 	//PLL set
-	{0x36e9, 0x20},
-	{0x36f9, 0x24},
+	{0x36e9, 0x54},
+	{0x36f9, 0x50},
+	{0x0100, 0x01},
+
+	//gain >= 2
+	{0x33fa, 0x02},
+	{0x3317, 0x14},
 
 	{REG_NULL, 0x00},
 };
@@ -395,14 +408,14 @@ static const struct sc132gs_mode supported_modes[] = {
 			.numerator = 10000,
 			.denominator = 300000,
 		},
-		.exp_def = 0x0148,
-		.hts_def = 0x06a0,
-		.vts_def = 0x084a,
+		.exp_def = 0x04ec,
+		.hts_def = 0x02ee*2,
+		.vts_def = 0x0578,
 		.link_freq_index = LINK_FREQ_180M_INDEX,
 		.pixel_rate      = PIXEL_RATE_WITH_180M,
 		.reg_list = sc132gs_2lane_10bit_regs,
 		.lanes    = 2,
-		.bus_fmt  = MEDIA_BUS_FMT_Y10_1X10,
+		.bus_fmt  = MEDIA_BUS_FMT_SBGGR10_1X10,
 	},
 
 	{
@@ -644,15 +657,19 @@ static int sc132gs_enum_frame_sizes(struct v4l2_subdev *sd,
 
 static int sc132gs_enable_test_pattern(struct sc132gs *sc132gs, u32 pattern)
 {
-	u32 val;
+	u32 val = 0;
+	int ret = 0;
 
+	ret = sc132gs_read_reg(sc132gs->client, SC132GS_REG_TEST_PATTERN,
+			       SC132GS_REG_VALUE_08BIT, &val);
 	if (pattern)
-		val = (pattern - 1) | SC132GS_TEST_PATTERN_ENABLE;
+		val |= SC132GS_TEST_PATTERN_BIT_MASK;
 	else
-		val = SC132GS_TEST_PATTERN_DISABLE;
+		val &= ~SC132GS_TEST_PATTERN_BIT_MASK;
 
-	return sc132gs_write_reg(sc132gs->client, SC132GS_REG_TEST_PATTERN,
-				 SC132GS_REG_VALUE_08BIT, val);
+	ret |= sc132gs_write_reg(sc132gs->client, SC132GS_REG_TEST_PATTERN,
+				SC132GS_REG_VALUE_08BIT, val);
+	return ret;
 }
 
 static void sc132gs_get_module_inf(struct sc132gs *sc132gs,
@@ -737,50 +754,75 @@ static long sc132gs_compat_ioctl32(struct v4l2_subdev *sd,
 static int sc132gs_set_ctrl_gain(struct sc132gs *sc132gs, u32 a_gain)
 {
 	int ret = 0;
-	u32 coarse_again, fine_again, fine_again_reg, coarse_again_reg;
+	u32 fine_again_reg, coarse_again_reg, fine_dgain_reg, coarse_dgain_reg;
 
 	if (a_gain < 0x20)
 		a_gain = 0x20;
-	if (a_gain > 0x391)
-		a_gain = 0x391;
+	if (a_gain > 0x6c80)
+		a_gain = 0x6c80;
 
 	if (a_gain < 0x3a) {/*1x~1.813*/
-		fine_again = a_gain;
-		coarse_again = 0x03;
-		fine_again_reg = fine_again & 0x3f;
-		coarse_again_reg = coarse_again & 0x3F;
-		if (fine_again_reg >= 0x39)
-			fine_again_reg = 0x39;
-	} else if (a_gain < 0x72) {/*1.813~3.568x*/
-		fine_again = (a_gain - 0x3a) * 1000 / 1755 + 0x20;
-		coarse_again = 0x23;
-		if (fine_again > 0x3f)
-			fine_again = 0x3f;
-		fine_again_reg = fine_again & 0x3f;
-		coarse_again_reg = coarse_again & 0x3F;
+		fine_again_reg = a_gain;
+		coarse_again_reg = 0x03;
+		fine_dgain_reg = 0x80;
+		coarse_dgain_reg = 0x00;
+	} else if (a_gain < 0x74) {/*1.813~3.568x*/
+		fine_again_reg = a_gain * 0x20 / 0x3a;
+		coarse_again_reg = 0x23;
+		fine_dgain_reg = 0x80;
+		coarse_dgain_reg = 0x00;
 	} else if (a_gain < 0xe8) { /*3.568x~7.250x*/
-		fine_again = (a_gain - 0x72) * 1000 / 3682 + 0x20;
-		coarse_again = 0x27;
-		if (fine_again > 0x3f)
-			fine_again = 0x3f;
-		fine_again_reg = fine_again & 0x3f;
-		coarse_again_reg = coarse_again & 0x3F;
+		fine_again_reg = a_gain * 0x20 / 0x74;
+		coarse_again_reg = 0x27;
+		fine_dgain_reg = 0x80;
+		coarse_dgain_reg = 0x00;
 	} else if (a_gain < 0x1d0) { /*7.250x~14.5x*/
-		fine_again = (a_gain - 0xe8) * 100 / 725 + 0x20;
-		coarse_again = 0x2f;
-		if (fine_again > 0x3f)
-			fine_again = 0x3f;
-		fine_again_reg = fine_again & 0x3f;
-		coarse_again_reg = coarse_again & 0x3F;
-	} else { /*14.5x~28.547*/
-		fine_again = (a_gain - 0x1d0) * 1000 / 14047 + 0x20;
-		coarse_again = 0x3f;
-		if (fine_again > 0x3f)
-			fine_again = 0x3f;
-		fine_again_reg = fine_again & 0x3f;
-		coarse_again_reg = coarse_again & 0x3F;
+		fine_again_reg = a_gain * 0x20 / 0xe8;
+		coarse_again_reg = 0x2f;
+		fine_dgain_reg = 0x80;
+		coarse_dgain_reg = 0x00;
+	} else if (a_gain < 0x3a0) { /*14.5x~28.547x*/
+		fine_again_reg = a_gain * 0x20 / 0x1d0;
+		coarse_again_reg = 0x3f;
+		fine_dgain_reg = 0x80;
+		coarse_dgain_reg = 0x00;
+	} else if (a_gain < 0x740) { /*again:28.547x, dgain: 1x~2x*/
+		fine_again_reg = 0x3f ;
+		coarse_again_reg = 0x3f;
+		fine_dgain_reg = a_gain * 0x8 / 0x3a;
+		if(fine_dgain_reg < 0x80) fine_dgain_reg =0x80;
+		else fine_dgain_reg = fine_dgain_reg & 0xfc;
+		coarse_dgain_reg = 0x00;
+	} else if (a_gain < 0xe80) { /*again:28.547x, dgain: 2x~4x*/
+		fine_again_reg = 0x3f ;
+		coarse_again_reg = 0x3f;
+		fine_dgain_reg = a_gain * 0x8 / 0x74;
+		if(fine_dgain_reg < 0x80) fine_dgain_reg =0x80;
+		else fine_dgain_reg = fine_dgain_reg & 0xfc;
+		coarse_dgain_reg = 0x01;
+	} else if (a_gain < 0x1d00) { /*again:28.547x, dgain: 4x~8x*/
+		fine_again_reg = 0x3f ;
+		coarse_again_reg = 0x3f;
+		fine_dgain_reg = a_gain * 0x8 / 0xe8;
+		if(fine_dgain_reg < 0x80) fine_dgain_reg =0x80;
+		else fine_dgain_reg = fine_dgain_reg & 0xfc;
+		coarse_dgain_reg = 0x03;
+	} else if (a_gain < 0x3a00) { /*again:28.547x, dgain: 8x~16x*/
+		fine_again_reg = 0x3f ;
+		coarse_again_reg = 0x3f;
+		fine_dgain_reg = a_gain * 0x8 / 0x1d0;
+		if(fine_dgain_reg < 0x80) fine_dgain_reg =0x80;
+		else fine_dgain_reg = fine_dgain_reg & 0xfc;
+		coarse_dgain_reg = 0x07;
+	} else { /*again:28.547x, dgain: 16x~31.5x*/
+		fine_again_reg = 0x3f ;
+		coarse_again_reg = 0x3f;
+		fine_dgain_reg = a_gain * 0x8 / 0x3a0;
+		if(fine_dgain_reg < 0x80) fine_dgain_reg =0x80;
+		else fine_dgain_reg = fine_dgain_reg & 0xfc;
+		coarse_dgain_reg = 0x0f;
 	}
-	ret |= sc132gs_write_reg(sc132gs->client,
+	ret = sc132gs_write_reg(sc132gs->client,
 		SC132GS_REG_COARSE_AGAIN,
 		SC132GS_REG_VALUE_08BIT,
 		coarse_again_reg);
@@ -788,6 +830,34 @@ static int sc132gs_set_ctrl_gain(struct sc132gs *sc132gs, u32 a_gain)
 		SC132GS_REG_FINE_AGAIN,
 		SC132GS_REG_VALUE_08BIT,
 		fine_again_reg);
+	ret |= sc132gs_write_reg(sc132gs->client,
+		SC132GS_REG_COARSE_DGAIN,
+		SC132GS_REG_VALUE_08BIT,
+		coarse_dgain_reg);
+	ret |= sc132gs_write_reg(sc132gs->client,
+		SC132GS_REG_FINE_DGAIN,
+		SC132GS_REG_VALUE_08BIT,
+		fine_dgain_reg);
+	if (a_gain < 0x40) {
+		ret |= sc132gs_write_reg(sc132gs->client,
+			0x33fa,
+			SC132GS_REG_VALUE_08BIT,
+			0x01);
+		ret |= sc132gs_write_reg(sc132gs->client,
+			0x3317,
+			SC132GS_REG_VALUE_08BIT,
+			0xf0);
+	} else {
+		ret |= sc132gs_write_reg(sc132gs->client,
+			0x33fa,
+			SC132GS_REG_VALUE_08BIT,
+			0x02);
+		ret |= sc132gs_write_reg(sc132gs->client,
+			0x3317,
+			SC132GS_REG_VALUE_08BIT,
+			0x0a);
+	}
+
 	return ret;
 }
 
@@ -1110,7 +1180,7 @@ static int sc132gs_set_ctrl(struct v4l2_ctrl *ctrl)
 	switch (ctrl->id) {
 	case V4L2_CID_VBLANK:
 		/* Update max exposure while meeting expected vblanking */
-		max = sc132gs->cur_mode->height + ctrl->val - 6;
+		max = sc132gs->cur_mode->height + ctrl->val - 8;
 		__v4l2_ctrl_modify_range(sc132gs->exposure,
 					 sc132gs->exposure->minimum, max,
 					 sc132gs->exposure->step,
@@ -1125,10 +1195,13 @@ static int sc132gs_set_ctrl(struct v4l2_ctrl *ctrl)
 	case V4L2_CID_EXPOSURE:
 		/* 4 least significant bits of expsoure are fractional part */
 		ret = sc132gs_write_reg(sc132gs->client, SC132GS_REG_EXPOSURE,
-			SC132GS_REG_VALUE_16BIT, ctrl->val << 4);
+					SC132GS_REG_VALUE_24BIT, ctrl->val << 4);
+
+		dev_dbg(&client->dev, "set exposure 0x%x \n",ctrl->val);
 		break;
 	case V4L2_CID_ANALOGUE_GAIN:
 		ret = sc132gs_set_ctrl_gain(sc132gs, ctrl->val);
+		dev_dbg(&client->dev, "set gain 0x%x \n",ctrl->val);
 		break;
 	case V4L2_CID_VBLANK:
 		ret = sc132gs_write_reg(sc132gs->client, SC132GS_REG_VTS,
@@ -1136,12 +1209,29 @@ static int sc132gs_set_ctrl(struct v4l2_ctrl *ctrl)
 					ctrl->val + sc132gs->cur_mode->height);
 		if (!ret)
 			sc132gs->cur_vts = ctrl->val + sc132gs->cur_mode->height;
-		sc132gs_modify_fps_info(sc132gs);
-		break;
+		if (sc132gs->cur_vts != sc132gs->cur_mode->vts_def)
+			sc132gs_modify_fps_info(sc132gs);
 		break;
 	case V4L2_CID_TEST_PATTERN:
 		ret = sc132gs_enable_test_pattern(sc132gs, ctrl->val);
 		break;
+	case V4L2_CID_HFLIP:
+		if (ctrl->val)
+			sc132gs->flip |= SC132GS_HFLIP_MASK;
+		else
+			sc132gs->flip &= ~SC132GS_HFLIP_MASK;
+		ret = sc132gs_write_reg(sc132gs->client, SC132GS_FLIP_REG,
+					SC132GS_REG_VALUE_08BIT, sc132gs->flip);
+		break;
+	case V4L2_CID_VFLIP:
+		if (ctrl->val)
+			sc132gs->flip |= SC132GS_VFLIP_MASK;
+		else
+			sc132gs->flip &= ~SC132GS_VFLIP_MASK;
+
+		ret = sc132gs_write_reg(sc132gs->client, SC132GS_FLIP_REG,
+					SC132GS_REG_VALUE_08BIT, sc132gs->flip);
+		break;
 	default:
 		dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
 			 __func__, ctrl->id, ctrl->val);
@@ -1195,7 +1285,7 @@ static int sc132gs_initialize_controls(struct sc132gs *sc132gs)
 				SC132GS_VTS_MAX - mode->height,
 				1, vblank_def);
 
-	exposure_max = mode->vts_def - 6;
+	exposure_max = mode->vts_def - 8;
 	sc132gs->exposure = v4l2_ctrl_new_std(handler, &sc132gs_ctrl_ops,
 				V4L2_CID_EXPOSURE, SC132GS_EXPOSURE_MIN,
 				exposure_max, SC132GS_EXPOSURE_STEP,
@@ -1210,7 +1300,12 @@ static int sc132gs_initialize_controls(struct sc132gs *sc132gs)
 				&sc132gs_ctrl_ops, V4L2_CID_TEST_PATTERN,
 				ARRAY_SIZE(sc132gs_test_pattern_menu) - 1,
 				0, 0, sc132gs_test_pattern_menu);
+	sc132gs->flip = 0;
+	sc132gs->h_flip = v4l2_ctrl_new_std(handler, &sc132gs_ctrl_ops,
+				V4L2_CID_HFLIP, 0, 1, 1, 0);
 
+	sc132gs->v_flip = v4l2_ctrl_new_std(handler, &sc132gs_ctrl_ops,
+				V4L2_CID_VFLIP, 0, 1, 1, 0);
 	if (handler->error) {
 		ret = handler->error;
 		dev_err(&sc132gs->client->dev,

drivers/mfd/display-serdes/core.h

@@ -404,6 +404,7 @@ struct serdes {
 	struct kthread_delayed_work reg_check_work;
 	bool use_reg_check_work;
 
+	bool dual_link;
 	bool split_mode_enable;
 	unsigned int reg_hw;
 	unsigned int reg_use;
@@ -459,6 +460,7 @@ void serdes_destroy_debugfs(struct serdes *serdes);
 extern struct serdes_chip_data serdes_bu18tl82_data;
 extern struct serdes_chip_data serdes_bu18rl82_data;
 extern struct serdes_chip_data serdes_max96745_data;
+extern struct serdes_chip_data serdes_max96749_data;
 extern struct serdes_chip_data serdes_max96752_data;
 extern struct serdes_chip_data serdes_max96755_data;
 extern struct serdes_chip_data serdes_max96772_data;

drivers/mfd/display-serdes/gpio.h

@@ -43,6 +43,7 @@ enum serdes_id {
 	ROHM_ID_BU18RL82,
 
 	MAXIM_ID_MAX96745,
+	MAXIM_ID_MAX96749,
 	MAXIM_ID_MAX96752,
 	MAXIM_ID_MAX96755,
 	MAXIM_ID_MAX96772,
@@ -107,6 +108,35 @@ enum max96745_gpio_list {
 	MAXIM_MAX96745_MFP25,
 };
 
+enum max96749_gpio_list {
+	MAXIM_MAX96749_MFP0 = 0,
+	MAXIM_MAX96749_MFP1,
+	MAXIM_MAX96749_MFP2,
+	MAXIM_MAX96749_MFP3,
+	MAXIM_MAX96749_MFP4,
+	MAXIM_MAX96749_MFP5,
+	MAXIM_MAX96749_MFP6,
+	MAXIM_MAX96749_MFP7,
+	MAXIM_MAX96749_MFP8,
+	MAXIM_MAX96749_MFP9,
+	MAXIM_MAX96749_MFP10,
+	MAXIM_MAX96749_MFP11,
+	MAXIM_MAX96749_MFP12,
+	MAXIM_MAX96749_MFP13,
+	MAXIM_MAX96749_MFP14,
+	MAXIM_MAX96749_MFP15,
+	MAXIM_MAX96749_MFP16,
+	MAXIM_MAX96749_MFP17,
+	MAXIM_MAX96749_MFP18,
+	MAXIM_MAX96749_MFP19,
+	MAXIM_MAX96749_MFP20,
+	MAXIM_MAX96749_MFP21,
+	MAXIM_MAX96749_MFP22,
+	MAXIM_MAX96749_MFP23,
+	MAXIM_MAX96749_MFP24,
+	MAXIM_MAX96749_MFP25,
+};
+
 enum max96752_gpio_list {
 	MAXIM_MAX96752_GPIO0 = 0,
 	MAXIM_MAX96752_GPIO1,

drivers/mfd/display-serdes/maxim/Kconfig

@@ -17,6 +17,12 @@ config SERDES_DISPLAY_CHIP_MAXIM_MAX96745
 	help
 	  To support maxim max96745 display serdes.
 
+config SERDES_DISPLAY_CHIP_MAXIM_MAX96749
+	tristate "maxim max96749 serdes"
+	default y
+	help
+	  To support maxim max96749 display serdes.
+
 config SERDES_DISPLAY_CHIP_MAXIM_MAX96752
 	tristate "maxim max96752 serdes"
 	default y

drivers/mfd/display-serdes/maxim/Makefile

@@ -3,6 +3,7 @@
 # maxim display serdes drivers configuration
 #
 obj-$(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96745)	+= maxim-max96745.o
+obj-$(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96749)	+= maxim-max96749.o
 obj-$(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96752)	+= maxim-max96752.o
 obj-$(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96755)	+= maxim-max96755.o
 obj-$(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96772)	+= maxim-max96772.o

drivers/mfd/display-serdes/maxim/maxim-max96749.h

@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * maxim-max96749.h -- register define for max96749 chip
+ *
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ *
+ * Author: ZITONG CAI <zitong.cai@rock-chips.com>
+ *
+ */
+
+#ifndef __MFD_SERDES_MAXIM_MAX96745_H__
+#define __MFD_SERDES_MAXIM_MAX96745_H__
+
+#include <linux/bitfield.h>
+
+#define GPIO_A_REG(gpio)	(0x0200 + ((gpio) * 8))
+#define GPIO_B_REG(gpio)	(0x0201 + ((gpio) * 8))
+#define GPIO_C_REG(gpio)	(0x0202 + ((gpio) * 8))
+#define GPIO_D_REG(gpio)	(0x0203 + ((gpio) * 8))
+
+/* 0005h */
+#define PU_LF3			BIT(3)
+#define PU_LF2			BIT(2)
+#define PU_LF1			BIT(1)
+#define PU_LF0			BIT(0)
+
+/* 0010h */
+#define RESET_ALL		BIT(7)
+#define SLEEP			BIT(3)
+
+/* 0011h */
+#define CXTP_B			BIT(2)
+#define CXTP_A			BIT(0)
+
+/* 0013h */
+#define LOCKED			BIT(3)
+#define ERROR			BIT(2)
+
+/* 0021h */
+#define	LINKA_LOCKED	BIT(2)
+#define	LINKB_LOCKED	BIT(3)
+
+/* 0026h */
+#define LF_0			GENMASK(2, 0)
+#define LF_1			GENMASK(6, 4)
+
+/* 0027h */
+#define LF_2			GENMASK(2, 0)
+#define LF_3			GENMASK(6, 4)
+
+/* 0028h, 0032h */
+#define LINK_EN			BIT(7)
+#define TX_RATE			GENMASK(3, 2)
+
+/* 0029h, 0033h */
+#define RESET_LINK		    BIT(0)
+#define RESET_ONESHOT		BIT(1)
+
+/* 0045h */
+#define DUAL_LINK_MODE		BIT(1)
+
+/* 002Ah, 0034h */
+#define LINK_LOCKED		BIT(0)
+
+/* 0076h, 0086h */
+#define DIS_REM_CC		BIT(7)
+
+/* 0100h */
+#define VID_LINK_SEL		GENMASK(2, 1)
+#define VID_TX_EN		BIT(0)
+
+/* 0101h */
+#define BPP			GENMASK(5, 0)
+
+/* 0102h */
+#define PCLKDET_A		BIT(7)
+#define DRIFT_ERR_A		BIT(6)
+#define OVERFLOW_A		BIT(5)
+#define FIFO_WARN_A		BIT(4)
+#define LIM_HEART		BIT(2)
+
+/* 0107h */
+#define VID_TX_ACTIVE_B		BIT(7)
+#define VID_TX_ACTIVE_A		BIT(6)
+
+/* 0108h */
+#define PCLKDET_B		BIT(7)
+#define DRIFT_ERR_B		BIT(6)
+#define OVERFLOW_B		BIT(5)
+#define FIFO_WARN_B		BIT(4)
+
+/* 0200h */
+#define RES_CFG			BIT(7)
+#define TX_COM_EN		BIT(5)
+#define GPIO_OUT		BIT(4)
+#define GPIO_IN			BIT(3)
+#define GPIO_OUT_DIS		BIT(0)
+
+/* 0201h */
+#define PULL_UPDN_SEL		GENMASK(7, 6)
+#define OUT_TYPE		BIT(5)
+#define GPIO_TX_ID		GENMASK(4, 0)
+
+/* 0202h */
+#define OVR_RES_CFG		BIT(7)
+#define IO_EDGE_RATE		GENMASK(6, 5)
+#define GPIO_RX_ID		GENMASK(4, 0)
+
+/* 0203h */
+#define GPIO_IO_RX_EN		BIT(5)
+#define GPIO_OUT_LGC		BIT(4)
+#define GPIO_RX_EN_B		BIT(3)
+#define GPIO_TX_EN_B		BIT(2)
+#define GPIO_RX_EN_A		BIT(1)
+#define GPIO_TX_EN_A		BIT(0)
+
+/* 0750h */
+#define FRCZEROPAD		GENMASK(7, 6)
+#define FRCZPEN			BIT(5)
+#define FRCSDGAIN		BIT(4)
+#define FRCSDEN			BIT(3)
+#define FRCGAIN			GENMASK(2, 1)
+#define FRCEN			BIT(0)
+
+/* 0751h */
+#define FRCDATAWIDTH		BIT(3)
+#define FRCASYNCEN		BIT(2)
+#define FRCHSPOL		BIT(1)
+#define FRCVSPOL		BIT(0)
+
+/* 0752h */
+#define FRCDCMODE		GENMASK(1, 0)
+
+/* 641Ah */
+#define DPRX_TRAIN_STATE	GENMASK(7, 4)
+
+/* 7000h */
+#define LINK_ENABLE		BIT(0)
+
+/* 7070h */
+#define MAX_LANE_COUNT		GENMASK(7, 0)
+
+/* 7074h */
+#define MAX_LINK_RATE		GENMASK(7, 0)
+
+#endif

drivers/mfd/display-serdes/maxim/maxim-max96772.c

@@ -14,11 +14,13 @@ static const struct regmap_range max96772_readable_ranges[] = {
 	regmap_reg_range(0x0000, 0x0800),
 	regmap_reg_range(0x1700, 0x1700),
 	regmap_reg_range(0x4100, 0x4100),
-	regmap_reg_range(0x6230, 0x6230),
+	regmap_reg_range(0x6000, 0x6230),
 	regmap_reg_range(0x7014, 0x7016),
 	regmap_reg_range(0xe75e, 0xe75e),
 	regmap_reg_range(0xe7c4, 0xe7c6),
 	regmap_reg_range(0xe776, 0xe7bf),
+	regmap_reg_range(0xe7d1, 0xe7d1),
+	regmap_reg_range(0xe7de, 0xe7de),
 };
 
 static const struct regmap_access_table max96772_readable_table = {
@@ -70,6 +72,23 @@ static int MAX96772_GPIO15_pins[] = {15};
 	.num_pins = ARRAY_SIZE(nm ## _pins), \
 }
 
+#define GROUP_DESC_CONFIG(nm) \
+{ \
+	.name = #nm, \
+	.pins = nm ## _pins, \
+	.num_pins = ARRAY_SIZE(nm ## _pins), \
+	.data = (void *)(const struct serdes_group_data []) { \
+		{ \
+			.configs = nm ## _configs, \
+			.num_configs = ARRAY_SIZE(nm ## _configs), \
+		} \
+	}, \
+}
+
+static const struct config_desc MAX96772_GPIO7_configs[] = {
+	{ 0x02, AUD_TX_EN, 0},
+};
+
 struct serdes_function_data {
 	u8 gpio_out_dis:1;
 	u8 gpio_tx_en:1;
@@ -169,7 +188,7 @@ static struct group_desc max96772_groups_desc[] = {
 	GROUP_DESC(MAX96772_GPIO4),
 	GROUP_DESC(MAX96772_GPIO5),
 	GROUP_DESC(MAX96772_GPIO6),
-	GROUP_DESC(MAX96772_GPIO7),
+	GROUP_DESC_CONFIG(MAX96772_GPIO7),
 
 	GROUP_DESC(MAX96772_GPIO8),
 	GROUP_DESC(MAX96772_GPIO9),
@@ -337,6 +356,70 @@ static const struct reg_sequence max96772_clk_ref[4][14] = {
 	}
 };
 
+static const struct reg_sequence max96772_clk_ssc[4][14] = {
+	{
+		{ 0xe7b2, 0x50 },
+		{ 0xe7b3, 0x00 },
+		{ 0xe7b4, 0x35 },
+		{ 0xe7b5, 0x42 },
+		{ 0xe7b6, 0x81 },
+		{ 0xe7b7, 0x30 },
+		{ 0xe7b8, 0x07 },
+		{ 0xe7b9, 0x10 },
+		{ 0xe7ba, 0x01 },
+		{ 0xe7bb, 0x00 },
+		{ 0xe7bc, 0x00 },
+		{ 0xe7bd, 0x00 },
+		{ 0xe7be, 0x52 },
+		{ 0xe7bf, 0x00 },
+	}, {
+		{ 0xe7b2, 0x50 },
+		{ 0xe7b3, 0x00 },
+		{ 0xe7b4, 0xd7 },
+		{ 0xe7b5, 0x45 },
+		{ 0xe7b6, 0x6b },
+		{ 0xe7b7, 0x20 },
+		{ 0xe7b8, 0x07 },
+		{ 0xe7b9, 0x00 },
+		{ 0xe7ba, 0x01 },
+		{ 0xe7bb, 0x00 },
+		{ 0xe7bc, 0x00 },
+		{ 0xe7bd, 0x00 },
+		{ 0xe7be, 0x52 },
+		{ 0xe7bf, 0x00 },
+	}, {
+		{ 0xe7b2, 0x30 },
+		{ 0xe7b3, 0x00 },
+		{ 0xe7b4, 0xd7 },
+		{ 0xe7b5, 0x45 },
+		{ 0xe7b6, 0x6b },
+		{ 0xe7b7, 0x20 },
+		{ 0xe7b8, 0x14 },
+		{ 0xe7b9, 0x00 },
+		{ 0xe7ba, 0x2e },
+		{ 0xe7bb, 0x00 },
+		{ 0xe7bc, 0x02 },
+		{ 0xe7bd, 0x01 },
+		{ 0xe7be, 0x32 },
+		{ 0xe7bf, 0x00 },
+	}, {
+		{ 0xe7b2, 0x30 },
+		{ 0xe7b3, 0x00 },
+		{ 0xe7b4, 0xd7 },
+		{ 0xe7b5, 0x45 },
+		{ 0xe7b6, 0x6b },
+		{ 0xe7b7, 0x20 },
+		{ 0xe7b8, 0x14 },
+		{ 0xe7b9, 0x00 },
+		{ 0xe7ba, 0x2e },
+		{ 0xe7bb, 0x00 },
+		{ 0xe7bc, 0x00 },
+		{ 0xe7bd, 0x00 },
+		{ 0xe7be, 0x32 },
+		{ 0xe7bf, 0x00 },
+	}
+};
+
 static int max96772_aux_dpcd_read(struct serdes *serdes, unsigned int reg, unsigned int *value)
 {
 	serdes_reg_write(serdes, 0xe778, reg & 0xff);
@@ -358,6 +441,35 @@ static int max96772_panel_prepare(struct serdes *serdes)
 	u32 vact, vsa, vfp, vbp;
 	u64 hwords, mvid;
 	bool hsync_pol, vsync_pol;
+	int ret;
+	u32 dpcd;
+	int link_rate;
+
+	if (!serdes->serdes_panel->link_rate || !serdes->serdes_panel->lane_count) {
+		ret = max96772_aux_dpcd_read(serdes, DP_MAX_LANE_COUNT, &dpcd);
+		if (ret) {
+			dev_err(serdes->dev, "failed to read max lane count\n");
+			return ret;
+		}
+
+		serdes->serdes_panel->lane_count = min_t(int, 4, dpcd & DP_MAX_LANE_COUNT_MASK);
+
+		ret = max96772_aux_dpcd_read(serdes, DP_MAX_LINK_RATE, &dpcd);
+		if (ret) {
+			dev_err(serdes->dev, "failed to read max link rate\n");
+			return ret;
+		}
+
+		serdes->serdes_panel->link_rate = min_t(int, dpcd, DP_LINK_BW_5_4);
+
+		ret = max96772_aux_dpcd_read(serdes, DP_MAX_DOWNSPREAD, &dpcd);
+		if (ret) {
+			dev_err(serdes->dev, "failed to read max downspread\n");
+			return ret;
+		}
+
+		serdes->serdes_panel->ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5);
+	}
 
 	serdes_reg_write(serdes, 0xe790, serdes->serdes_panel->link_rate);
 	serdes_reg_write(serdes, 0xe792, serdes->serdes_panel->lane_count);
@@ -373,20 +485,46 @@ static int max96772_panel_prepare(struct serdes *serdes)
 		 serdes->serdes_panel->link_rate, serdes->serdes_panel->lane_count,
 		 serdes->serdes_panel->ssc);
 
-	switch (serdes->serdes_panel->link_rate) {
-	case DP_LINK_BW_5_4:
-		serdes_multi_reg_write(serdes, max96772_clk_ref[2],
-				       ARRAY_SIZE(max96772_clk_ref[2]));
+	if (serdes->serdes_panel->ssc) {
+		switch (serdes->serdes_panel->link_rate) {
+		case DP_LINK_BW_8_1:
+			serdes_multi_reg_write(serdes, max96772_clk_ssc[3],
+						    ARRAY_SIZE(max96772_clk_ssc[3]));
 		break;
-	case DP_LINK_BW_2_7:
-		serdes_multi_reg_write(serdes, max96772_clk_ref[1],
-				       ARRAY_SIZE(max96772_clk_ref[1]));
+		case DP_LINK_BW_5_4:
+			serdes_multi_reg_write(serdes, max96772_clk_ssc[2],
+						    ARRAY_SIZE(max96772_clk_ssc[2]));
 		break;
-	case DP_LINK_BW_1_62:
-	default:
-		serdes_multi_reg_write(serdes, max96772_clk_ref[0],
-				       ARRAY_SIZE(max96772_clk_ref[0]));
+		case DP_LINK_BW_2_7:
+			serdes_multi_reg_write(serdes, max96772_clk_ssc[1],
+						    ARRAY_SIZE(max96772_clk_ssc[1]));
 		break;
+		case DP_LINK_BW_1_62:
+		default:
+			serdes_multi_reg_write(serdes, max96772_clk_ssc[0],
+						    ARRAY_SIZE(max96772_clk_ssc[0]));
+		break;
+		}
+	} else {
+		switch (serdes->serdes_panel->link_rate) {
+		case DP_LINK_BW_8_1:
+			serdes_multi_reg_write(serdes, max96772_clk_ref[3],
+					       ARRAY_SIZE(max96772_clk_ref[3]));
+			break;
+		case DP_LINK_BW_5_4:
+			serdes_multi_reg_write(serdes, max96772_clk_ref[2],
+					       ARRAY_SIZE(max96772_clk_ref[2]));
+			break;
+		case DP_LINK_BW_2_7:
+			serdes_multi_reg_write(serdes, max96772_clk_ref[1],
+					       ARRAY_SIZE(max96772_clk_ref[1]));
+			break;
+		case DP_LINK_BW_1_62:
+		default:
+			serdes_multi_reg_write(serdes, max96772_clk_ref[0],
+					       ARRAY_SIZE(max96772_clk_ref[0]));
+			break;
+		}
 	}
 
 	vact = mode->vdisplay;
@@ -428,9 +566,11 @@ static int max96772_panel_prepare(struct serdes *serdes)
 	serdes_reg_write(serdes, 0xe7a4, hwords);
 	serdes_reg_write(serdes, 0xe7a5, hwords >> 8);
 
-	/* MVID = (PCLK x NVID) x 10 / Link Rate */
+	/* MVID = (PCLK_in_MHz x NVID)/(Link_Rate_in_GBs * 100) */
+	link_rate = drm_dp_bw_code_to_link_rate(serdes->serdes_panel->link_rate);
 	mvid = DIV_ROUND_CLOSEST_ULL((u64)mode->clock * 32768,
-				     drm_dp_bw_code_to_link_rate(serdes->serdes_panel->link_rate));
+				     link_rate);
+
 	serdes_reg_write(serdes, 0xe7a6, mvid & 0xff);
 	serdes_reg_write(serdes, 0xe7a7, (mvid >> 8) & 0xff);
 
@@ -568,7 +708,6 @@ static int max96772_pinctrl_set_mux(struct serdes *serdes,
 
 		for (i = 0; i < gdata->num_configs; i++) {
 			const struct config_desc *config = &gdata->configs[i];
-
 			serdes_set_bits(serdes, config->reg,
 					config->mask, config->val);
 		}
@@ -730,21 +869,101 @@ static struct serdes_chip_pinctrl_ops max96772_pinctrl_ops = {
 
 static int max96772_gpio_direction_input(struct serdes *serdes, int gpio)
 {
+	struct serdes_pinctrl *pinctrl = serdes->pinctrl;
+	struct group_desc *grp;
+	int i;
+
+	grp = pinctrl_generic_get_group(pinctrl->pctl, gpio);
+	if (!grp)
+		return -EINVAL;
+
+	if (grp->data) {
+		struct serdes_group_data *gdata = grp->data;
+
+		for (i = 0; i < gdata->num_configs; i++) {
+			const struct config_desc *config = &gdata->configs[i];
+
+			serdes_set_bits(serdes, config->reg,
+					config->mask, config->val);
+		}
+	}
+
+	serdes_set_bits(serdes, GPIO_A_REG(gpio),
+					GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN,
+					FIELD_PREP(GPIO_OUT_DIS, 0) |
+					FIELD_PREP(GPIO_RX_EN, 1) |
+					FIELD_PREP(GPIO_TX_EN, 0));
+
+	serdes_set_bits(serdes, GPIO_B_REG(gpio),
+					OUT_TYPE,
+					FIELD_PREP(OUT_TYPE, 1));
+
+	SERDES_DBG_CHIP("%s: serdes chip %s gpio=%d\n",
+		__func__, serdes->chip_data->name, gpio);
+
 	return 0;
 }
 
 static int max96772_gpio_direction_output(struct serdes *serdes, int gpio, int value)
 {
+	struct serdes_pinctrl *pinctrl = serdes->pinctrl;
+	struct group_desc *grp;
+	int i;
+
+	grp = pinctrl_generic_get_group(pinctrl->pctl, gpio);
+	if (!grp)
+		return -EINVAL;
+
+	if (grp->data) {
+		struct serdes_group_data *gdata = grp->data;
+
+		for (i = 0; i < gdata->num_configs; i++) {
+			const struct config_desc *config = &gdata->configs[i];
+
+			serdes_set_bits(serdes, config->reg,
+					config->mask, config->val);
+		}
+	}
+
+	serdes_set_bits(serdes, GPIO_A_REG(gpio),
+					GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN | GPIO_OUT,
+					FIELD_PREP(GPIO_OUT_DIS, 0) |
+					FIELD_PREP(GPIO_RX_EN, 0) |
+					FIELD_PREP(GPIO_TX_EN, 0) |
+					FIELD_PREP(GPIO_OUT, value));
+
+	serdes_set_bits(serdes,
+					GPIO_B_REG(gpio),
+					OUT_TYPE,
+					FIELD_PREP(OUT_TYPE, 1));
+
+	SERDES_DBG_CHIP("%s: serdes chip %s gpio=%d value=%d\n",
+		__func__, serdes->chip_data->name, gpio, value);
+
 	return 0;
 }
 
 static int max96772_gpio_get_level(struct serdes *serdes, int gpio)
 {
-	return 0;
+	unsigned int value;
+
+	serdes_reg_read(serdes, GPIO_A_REG(gpio), &value);
+
+	value &= GPIO_IN;
+	SERDES_DBG_CHIP("%s: serdes chip %s gpio=%d\n",
+		__func__, serdes->chip_data->name, gpio, value);
+
+	return value;
 }
 
 static int max96772_gpio_set_level(struct serdes *serdes, int gpio, int value)
 {
+	serdes_set_bits(serdes, GPIO_A_REG(gpio), GPIO_OUT,
+			FIELD_PREP(GPIO_OUT, value));
+
+	SERDES_DBG_CHIP("%s: serdes chip %s gpio=%d value=%d\n",
+		__func__, serdes->chip_data->name, gpio, value);
+
 	return 0;
 }
 

drivers/mfd/display-serdes/maxim/maxim-max96772.h

@@ -11,28 +11,55 @@
 #ifndef __MFD_SERDES_MAXIM_MAX96772_H__
 #define __MFD_SERDES_MAXIM_MAX96772_H__
 
-#define GPIO_A_REG(gpio)	(0x02b0 + ((gpio) * 3))
-#define GPIO_B_REG(gpio)	(0x02b1 + ((gpio) * 3))
-#define GPIO_C_REG(gpio)	(0x02b2 + ((gpio) * 3))
+#define GPIO_A_REG(gpio)      (0x02b0 + ((gpio) * 3))
+#define GPIO_B_REG(gpio)      (0x02b1 + ((gpio) * 3))
+#define GPIO_C_REG(gpio)      (0x02b2 + ((gpio) * 3))
 
+/* 0002h */
+#define VID_EN_U              BIT(7)
+#define VID_EN_Z              BIT(6)
+#define VID_EN_Y              BIT(5)
+#define VID_EN_X              BIT(4)
+#define AUD_TX_EN             BIT(2)
+
+/* 0004h */
+#define LINK_EN_B             BIT(5)
+#define LINK_EN_A             BIT(4)
+
+/* 0010h */
+#define RESET_ALL             BIT(7)
+#define RESET_LINK            BIT(6)
+#define RESET_ONESHOT         BIT(5)
+#define AUTO_LINK             BIT(4)
+#define SLEEP                 BIT(3)
+#define REG_ENABLE            BIT(2)
+#define LINK_CFG              GENMASK(1, 0)
+
+/* 0013h */
+#define LINK_MODE             BIT(4)
+#define LOCKED                BIT(3)
+
+/* 001fh */
+#define LINKA_LOCKED          BIT(4)
+#define LINKB_LOCKED          BIT(5)
 
 /* 02b0h */
-#define RES_CFG			BIT(7)
-#define RSVD			BIT(6)
-#define TX_COMP_EN		BIT(5)
-#define GPIO_OUT		BIT(4)
-#define GPIO_IN			BIT(3)
-#define GPIO_RX_EN		BIT(2)
-#define GPIO_TX_EN		BIT(1)
-#define GPIO_OUT_DIS		BIT(0)
+#define RES_CFG               BIT(7)
+#define RSVD                  BIT(6)
+#define TX_COMP_EN            BIT(5)
+#define GPIO_OUT              BIT(4)
+#define GPIO_IN               BIT(3)
+#define GPIO_RX_EN            BIT(2)
+#define GPIO_TX_EN            BIT(1)
+#define GPIO_OUT_DIS          BIT(0)
 
 /* 02b1h */
-#define PULL_UPDN_SEL		GENMASK(7, 6)
-#define OUT_TYPE		BIT(5)
-#define GPIO_TX_ID		GENMASK(4, 0)
+#define PULL_UPDN_SEL         GENMASK(7, 6)
+#define OUT_TYPE              BIT(5)
+#define GPIO_TX_ID            GENMASK(4, 0)
 
 /* 02b2h */
-#define OVR_RES_CFG		BIT(7)
-#define GPIO_RX_ID		GENMASK(4, 0)
+#define OVR_RES_CFG           BIT(7)
+#define GPIO_RX_ID            GENMASK(4, 0)
 
 #endif

drivers/mfd/display-serdes/serdes-bridge-split.c

@@ -327,6 +327,7 @@ static const struct of_device_id serdes_bridge_split_of_match[] = {
 	{ .compatible = "rohm,bu18tl82-bridge-split", },
 	{ .compatible = "rohm,bu18rl82-bridge-split", },
 	{ .compatible = "maxim,max96745-bridge-split", },
+	{ .compatible = "maxim,max96749-bridge-split", },
 	{ .compatible = "maxim,max96755-bridge-split", },
 	{ .compatible = "maxim,max96752-bridge-split", },
 	{ .compatible = "maxim,max96789-bridge-split", },

drivers/mfd/display-serdes/serdes-bridge.c

@@ -326,6 +326,7 @@ static const struct of_device_id serdes_bridge_of_match[] = {
 	{ .compatible = "rohm,bu18tl82-bridge", },
 	{ .compatible = "rohm,bu18rl82-bridge", },
 	{ .compatible = "maxim,max96745-bridge", },
+	{ .compatible = "maxim,max96749-bridge", },
 	{ .compatible = "maxim,max96755-bridge", },
 	{ .compatible = "maxim,max96789-bridge", },
 	{ .compatible = "rockchip,rkx111-bridge", },

drivers/mfd/display-serdes/serdes-core.c

@@ -49,6 +49,21 @@ static const struct mfd_cell serdes_max96745_devs[] = {
 	},
 };
 
+static const struct mfd_cell serdes_max96749_devs[] = {
+	{
+		.name = "serdes-pinctrl",
+		.of_compatible = "maxim,max96749-pinctrl",
+	},
+	{
+		.name = "serdes-bridge",
+		.of_compatible = "maxim,max96749-bridge",
+	},
+	{
+		.name = "serdes-bridge-split",
+		.of_compatible = "maxim,max96749-bridge-split",
+	},
+};
+
 static const struct mfd_cell serdes_max96755_devs[] = {
 	{
 		.name = "serdes-pinctrl",
@@ -364,6 +379,10 @@ int serdes_device_init(struct serdes *serdes)
 		serdes_devs = serdes_max96745_devs;
 		mfd_num = ARRAY_SIZE(serdes_max96745_devs);
 		break;
+	case MAXIM_ID_MAX96749:
+		serdes_devs = serdes_max96749_devs;
+		mfd_num = ARRAY_SIZE(serdes_max96749_devs);
+		break;
 	case MAXIM_ID_MAX96752:
 		serdes_devs = serdes_max96752_devs;
 		mfd_num = ARRAY_SIZE(serdes_max96752_devs);

drivers/mfd/display-serdes/serdes-gpio.c

@@ -209,6 +209,7 @@ static const struct of_device_id serdes_gpio_of_match[] = {
 	{ .compatible = "rohm,bu18tl82-gpio", },
 	{ .compatible = "rohm,bu18rl82-gpio", },
 	{ .compatible = "maxim,max96745-gpio", },
+	{ .compatible = "maxim,max96749-gpio", },
 	{ .compatible = "maxim,max96752-gpio", },
 	{ .compatible = "maxim,max96755-gpio", },
 	{ .compatible = "maxim,max96772-gpio", },

drivers/mfd/display-serdes/serdes-i2c.c

@@ -310,6 +310,8 @@ static int serdes_get_init_seq(struct serdes *serdes)
 		return err;
 	}
 
+	serdes->dual_link = of_property_read_bool(dev->of_node, "dual-link");
+
 	/* init ser register(not des register) more early if uboot logo disabled */
 	serdes->route_enable = of_property_read_bool(dev->of_node, "route-enable");
 	if ((!serdes->route_enable) && (serdes->chip_data->serdes_type == TYPE_SER)) {
@@ -540,6 +542,9 @@ static const struct of_device_id serdes_of_match[] = {
 #if IS_ENABLED(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96745)
 	{ .compatible = "maxim,max96745", .data = &serdes_max96745_data },
 #endif
+#if IS_ENABLED(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96749)
+	{ .compatible = "maxim,max96749", .data = &serdes_max96749_data },
+#endif
 #if IS_ENABLED(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96752)
 	{ .compatible = "maxim,max96752", .data = &serdes_max96752_data },
 #endif

drivers/mfd/display-serdes/serdes-panel-split.c

@@ -148,10 +148,6 @@ static int serdes_panel_split_parse_dt(struct serdes_panel_split *serdes_panel_s
 	serdes_panel_split->width_mm = panel_size[0];
 	serdes_panel_split->height_mm = panel_size[1];
 
-	serdes_panel_split->link_rate = link_rate_count_ssc[0];
-	serdes_panel_split->lane_count = link_rate_count_ssc[1];
-	serdes_panel_split->ssc = link_rate_count_ssc[2];
-
 	if (of_find_property(dev->of_node, "panel-size", &len)) {
 		len /= sizeof(unsigned int);
 		ret = of_property_read_u32_array(dev->of_node, "panel-size",

drivers/mfd/display-serdes/serdes-panel.c

@@ -147,10 +147,6 @@ static int serdes_panel_parse_dt(struct serdes_panel *serdes_panel)
 	serdes_panel->width_mm = panel_size[0];
 	serdes_panel->height_mm = panel_size[1];
 
-	serdes_panel->link_rate = link_rate_count_ssc[0];
-	serdes_panel->lane_count = link_rate_count_ssc[1];
-	serdes_panel->ssc = link_rate_count_ssc[2];
-
 	if (of_find_property(dev->of_node, "panel-size", &len)) {
 		len /= sizeof(unsigned int);
 		if (len != 2) {

drivers/mfd/display-serdes/serdes-pinctrl.c

@@ -30,6 +30,13 @@ static const struct mfd_cell serdes_gpio_max96745_devs[] = {
 	},
 };
 
+static const struct mfd_cell serdes_gpio_max96749_devs[] = {
+	{
+		.name = "serdes-gpio",
+		.of_compatible = "maxim,max96749-gpio",
+	},
+};
+
 static const struct mfd_cell serdes_gpio_max96755_devs[] = {
 	{
 		.name = "serdes-gpio",
@@ -173,6 +180,10 @@ static int serdes_pinctrl_gpio_init(struct serdes *serdes)
 		serdes_devs = serdes_gpio_max96745_devs;
 		mfd_num = ARRAY_SIZE(serdes_gpio_max96745_devs);
 		break;
+	case MAXIM_ID_MAX96749:
+		serdes_devs = serdes_gpio_max96749_devs;
+		mfd_num = ARRAY_SIZE(serdes_gpio_max96749_devs);
+		break;
 	case MAXIM_ID_MAX96752:
 		serdes_devs = serdes_gpio_max96752_devs;
 		mfd_num = ARRAY_SIZE(serdes_gpio_max96752_devs);

drivers/pwm/Kconfig

@@ -507,6 +507,13 @@ config PWM_ROCKCHIP_TEST
 	  whether it is about the generic framework or the functions
 	  supported by Rockchip PWM.
 
+config PWM_R7F701
+	tristate "R7F701 PWM support"
+	help
+	  This is a MCU for controlling brightness on the screen, which
+	  adjusts brightness by writing corresponding registers through I2C.
+	  If you don't have this MCU in your design, choose N.
+
 config PWM_SAMSUNG
 	tristate "Samsung PWM support"
 	depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST

drivers/pwm/Makefile

@@ -46,6 +46,7 @@ obj-$(CONFIG_PWM_RCAR)		+= pwm-rcar.o
 obj-$(CONFIG_PWM_RENESAS_TPU)	+= pwm-renesas-tpu.o
 obj-$(CONFIG_PWM_ROCKCHIP)	+= pwm-rockchip.o
 obj-$(CONFIG_PWM_ROCKCHIP_TEST)	+= pwm-rockchip-test.o
+obj-$(CONFIG_PWM_R7F701)	+= pwm-r7f701.o
 obj-$(CONFIG_PWM_SAMSUNG)	+= pwm-samsung.o
 obj-$(CONFIG_PWM_SIFIVE)	+= pwm-sifive.o
 obj-$(CONFIG_PWM_SL28CPLD)	+= pwm-sl28cpld.o

drivers/pwm/pwm-r7f701.c

@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * serdes-i2c.c  --  Control screen brightness
+ *
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ *
+ * Author: ZITONG CAI <zitong.cai@rock-chips.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/pwm.h>
+#include <linux/of_device.h>
+#include <linux/i2c.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/gpio/driver.h>
+#include <linux/gpio/consumer.h>
+
+#define PWM_MAX_LEVEL                            0x64
+
+#define DISPLAY_STATUS                           0x40
+#define LVDS_LOCK_STATUS                         0x41
+#define CUR_BRIGHTNESS_LEVEL                     0x42
+#define OLED_FAULT_RECORD                        0x43
+#define PCB_TEMP_STATUS                          0x44
+#define OLED_TEMP_STATUS                         0x45
+#define CID_POWER_STATUS                         0x46
+#define CID_HARDWARE_VERSION                     0x47
+#define CID_SOFT_APP_VERSION                     0x48
+#define CID_BOOTLOADER_VERSION                   0x49
+#define CID_FUALT_RECORD                         0x4a
+#define CID_VOLTAGE_VALUE                        0x4b
+#define CID_CURRENT_MODE_STATUS                  0x4c
+#define CID_ENTER_AUTO_CAUSE                     0x4d
+#define CID_CAN_STATUS                           0x4e
+
+
+#define REQUEST_DISPLAY_STATUS                   0x80
+#define REQUEST_LVDS_LOCK_STATUS                 0x81
+#define REQUEST_BRIGHTNESS_LEVEL                 0x82
+#define REQUEST_OLED_FAULT_RECORD                0x83
+#define REQUEST_PCB_TEMP_STATUS                  0x84
+#define REQUEST_OLED_TEMP_STATUS                 0x85
+#define REQUEST_CID_POWER_STATE                  0x86
+#define REQUEST_CID_HARDWARE_VERSION             0x87
+#define REQUEST_CID_SOFT_APP_VERSION             0x88
+#define REQUEST_CID_BOOTLOADER_VERSION           0x89
+#define REQUEST_CID_FUALT_RECORD                 0x8a
+#define REQUEST_CID_VOLTAGE_VALUE                0x8b
+#define REQUEST_CID_CURRENT_MODE_STATUS          0x8c
+#define REQUEST_CID_ENTER_AUTO_CAUSE             0x8d
+#define REQUEST_DISPLAY_STATUS_SET               0x8e
+#define REQUEST_CID_BRIGHTNESS_SET               0x8f
+#define REQUEST_IDCM_WRITE_HEART                 0x90
+#define REQUEST_CID_CAN_STATUS                   0x91
+#define REQUEST_IDCM_SEND_CRC                    0x92
+
+enum {
+	DISPLAY_OFF,
+	DISPLAY_ON
+};
+
+struct r7f701_pwm_chip {
+	struct pwm_chip	chip;
+	struct device	*dev;
+	struct regmap *regmap;
+
+};
+
+static bool r7f701_is_writeable_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case 0x80 ... 0x92:
+		return true;
+	}
+	return false;
+}
+
+static bool r7f701_is_readable_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case 0x40 ... 0x4e:
+		return true;
+	}
+	return false;
+}
+
+static bool r7f701_is_volatile_reg(struct device *dev, unsigned int reg)
+{
+	return true;
+}
+
+
+static const struct regmap_config r7f701_regmap_config = {
+	.name = "r7f701",
+	.reg_bits = 8,
+	.val_bits = 8,
+	.writeable_reg = r7f701_is_writeable_reg,
+	.readable_reg = r7f701_is_readable_reg,
+	.volatile_reg = r7f701_is_volatile_reg,
+	.cache_type = REGCACHE_RBTREE,
+	.max_register = 0x92,
+};
+
+static inline struct r7f701_pwm_chip *to_r7f701_pwm_chip(struct pwm_chip *chip)
+{
+	return container_of(chip, struct r7f701_pwm_chip, chip);
+}
+
+static int r7f701_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+	u64 duty_ns, u64 period_ns)
+{
+	u8 reg = 0;
+	u64 div = 0;
+	u8 level = 0;
+	int ret = 0;
+	u8 data[7] = {0};
+	struct r7f701_pwm_chip *r7f701 = to_r7f701_pwm_chip(chip);
+
+	div = duty_ns * PWM_MAX_LEVEL;
+	level = DIV_ROUND_CLOSEST_ULL(div, period_ns);
+
+	reg = REQUEST_DISPLAY_STATUS_SET;
+	data[0] = DISPLAY_ON;
+	data[1] = level;
+	data[6] = reg ^ data[0] ^ data[1];
+	ret |= regmap_bulk_write(r7f701->regmap, reg, data, ARRAY_SIZE(data));
+	memset(data, 0, sizeof(data));
+
+	reg = REQUEST_CID_BRIGHTNESS_SET;
+	data[0] = level;
+	data[6] = reg ^ data[0];
+	ret |= regmap_bulk_write(r7f701->regmap, reg, data, ARRAY_SIZE(data));
+
+	dev_dbg(chip->dev, "%s: pwm chip BRIGHTNESS_SET level 0x%x ret=%d\n", __func__, level, ret);
+
+	return 0;
+}
+
+static int r7f701_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	dev_dbg(chip->dev, "%s: pwm chip\n", __func__);
+
+	return 0;
+}
+
+static void r7f701_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct r7f701_pwm_chip *r7f701 = to_r7f701_pwm_chip(chip);
+	int ret = 0;
+	u8 reg = 0;
+	u8 data[7] = {0};
+
+	reg = REQUEST_DISPLAY_STATUS_SET;
+	data[0] = DISPLAY_OFF;
+	data[6] = reg ^ data[0];
+	ret = regmap_bulk_write(r7f701->regmap, reg, data, ARRAY_SIZE(data));
+
+	dev_dbg(chip->dev, "%s: pwm chip ret=%d\n", __func__, ret);
+}
+
+static int r7f701_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+	const struct pwm_state *state)
+{
+	int err;
+
+	if (state->polarity != PWM_POLARITY_NORMAL)
+		return -EINVAL;
+
+	if (!state->enabled) {
+		if (pwm->state.enabled)
+			r7f701_pwm_disable(chip, pwm);
+
+		return 0;
+	}
+
+	err = r7f701_pwm_config(chip, pwm, state->duty_cycle, state->period);
+	if (err)
+		return err;
+
+	if (!pwm->state.enabled)
+		return r7f701_pwm_enable(chip, pwm);
+
+	return 0;
+}
+
+static int r7f701_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+				 struct pwm_state *state)
+{
+	state->enabled = true;
+	state->polarity = PWM_POLARITY_NORMAL;
+
+	dev_dbg(chip->dev, "%s: pwm chip\n", __func__);
+
+	return 0;
+}
+
+static const struct pwm_ops r7f701_pwm_ops = {
+	.apply = r7f701_pwm_apply,
+	.get_state = r7f701_pwm_get_state,
+	.owner = THIS_MODULE,
+};
+
+static const struct of_device_id pwm_of_match[] = {
+	{ .compatible = "r7f701-pwm", .data = 0},
+	{ }
+};
+
+static int pwm_probe(struct i2c_client *client,
+	const struct i2c_device_id *id)
+{
+	struct device *dev = &client->dev;
+	struct r7f701_pwm_chip *r7f701;
+	int ret = 0;
+
+	r7f701 = devm_kzalloc(dev, sizeof(*r7f701), GFP_KERNEL);
+	if (!r7f701)
+		return -ENOMEM;
+
+	r7f701->dev = dev;
+	r7f701->chip.dev = dev;
+	r7f701->chip.ops = &r7f701_pwm_ops;
+	r7f701->chip.npwm = 1;
+
+	i2c_set_clientdata(client, r7f701);
+	dev_set_drvdata(dev, r7f701);
+
+	r7f701->regmap = devm_regmap_init_i2c(client, &r7f701_regmap_config);
+	if (IS_ERR(r7f701->regmap)) {
+		dev_err(dev, "%s: Failed to allocate r7f701 register map\n", __func__);
+		return PTR_ERR(r7f701->regmap);
+	}
+
+	ret = devm_pwmchip_add(dev, &r7f701->chip);
+	if (ret < 0) {
+		dev_err(dev, "%s: pwmchip_add() failed: %d\n", __func__, ret);
+		return ret;
+	}
+
+	dev_dbg(dev, "%s successful\n", __func__);
+
+	return 0;
+}
+
+static struct i2c_driver r7f701_i2c_driver = {
+	.driver		= {
+		.name	= "r7f701-pwm",
+		.of_match_table = of_match_ptr(pwm_of_match),
+	},
+	.probe		= pwm_probe,
+};
+
+static int __init r7f701_i2c_init(void)
+{
+	int ret;
+
+	ret = i2c_add_driver(&r7f701_i2c_driver);
+	if (ret != 0)
+		pr_err("Failed to register r7f701 I2C driver: %d\n", ret);
+
+	return ret;
+}
+
+static void __exit r7f701_i2c_exit(void)
+{
+	i2c_del_driver(&r7f701_i2c_driver);
+}
+
+subsys_initcall(r7f701_i2c_init);
+module_exit(r7f701_i2c_exit);
+
+MODULE_AUTHOR("ZITONG CAI <zitong.cai@rock-chips.com>");
+MODULE_DESCRIPTION("display pwm interface");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:r7f701-PWM");

drivers/usb/host/xhci-mem.c

@@ -1544,7 +1544,8 @@ int xhci_endpoint_init(struct xhci_hcd *xhci,
 		err_count = 3;
 	/* HS bulk max packet should be 512, FS bulk supports 8, 16, 32 or 64 */
 	if (usb_endpoint_xfer_bulk(&ep->desc)) {
-		if (udev->speed == USB_SPEED_HIGH)
+		/* xHCI 1.1 can support HS bulk max packet smaller than 512 */
+		if (udev->speed == USB_SPEED_HIGH && xhci->hci_version < 0x110)
 			max_packet = 512;
 		if (udev->speed == USB_SPEED_FULL) {
 			max_packet = rounddown_pow_of_two(max_packet);

include/dt-bindings/display/rockchip_vop.h

@@ -28,6 +28,22 @@
 
 #define	ROCKCHIP_VOP2_PHY_ID_INVALID	-1
 
+/*
+ * FBD: Fast Boot Display
+ *
+ * ROCKCHIP_DRM_FBD_FROM_UBOOT:
+ *     show logo.bmp from uboot and show logo_kernel.bmp after enter kernel;
+ * ROCKCHIP_DRM_FBD_FROM_UBOOT_TO_RTOS:
+ *     crtc/connector/panel will be init at uboot, and update plane at rtos;
+ * ROCKCHIP_DRM_FBD_FROM_RTOS:
+ *     crtc/connector/panel will be init at rtos, uboot no need to do any hardware
+ *     config, but need to pass the logic state to kernel to ensure pd/clk/drm
+ *     state is continuous.
+ */
+#define ROCKCHIP_DRM_FBD_FROM_UBOOT		0
+#define ROCKCHIP_DRM_FBD_FROM_UBOOT_TO_RTOS	1
+#define ROCKCHIP_DRM_FBD_FROM_RTOS		2
+
 /* mcu_data[23:0] */
 #define ROCKCHIP_MCU_DATA_MAP_DATA_1x24			0
 /*