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deinterlace: fix blend setting err [1/1]

Browse Source 
PD#SWPL-8980

Problem:
0x170d[16] can't set;

Solution:
Correct logic errors according to Feijun's suggestions

Verify:
TL1

Change-Id: If1ba9494d49b5614aac7571c3ee0e6ddb3fb6245
Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
This commit is contained in:
Jihong Sui
2019-09-17 13:48:14 +08:00
committed by Tao Zeng
parent 25723698d7
commit ab4677495e
1 changed files with 8 additions and 4 deletions
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12
drivers/amlogic/media/deinterlace/deinterlace_hw.c
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@@ -3842,25 +3842,29 @@ void pulldown_vof_win_config(struct pulldown_detected_s *wins)
(wins->regs[0].win_ve > wins->regs[0].win_vs)
? 1 : 0, 16, 1);
DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
wins->regs[0].blend_mode, 8, 2);
/*wins->regs[0].blend_mode*/
0x03, 8, 2);
DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
(wins->regs[1].win_ve > wins->regs[1].win_vs)
? 1 : 0, 17, 1);
DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
wins->regs[1].blend_mode, 10, 2);
/*wins->regs[1].blend_mode*/
0x03, 10, 2);
DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
(wins->regs[2].win_ve > wins->regs[2].win_vs)
? 1 : 0, 18, 1);
DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
wins->regs[2].blend_mode, 12, 2);
/*wins->regs[2].blend_mode*/
0x03, 12, 2);
DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
(wins->regs[3].win_ve > wins->regs[3].win_vs)
? 1 : 0, 19, 1);
DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL,
wins->regs[3].blend_mode, 14, 2);
/*wins->regs[3].blend_mode*/
0x03, 14, 2);
}