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ARM: dts: rv1126: uvc: fix cpll to 491520000

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Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: Ibd6df2bbcb24ea5ba72c40a8146d8a6d1c3e32a7
This commit is contained in:
Huang zhibao
2021-01-15 12:49:04 +08:00
committed by Tao Huang
parent 0eae5a230c
commit acfeb3f707
2 changed files with 38 additions and 0 deletions
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19
arch/arm/boot/dts/rv1126-ai-cam.dtsi
View File

@@ -99,6 +99,25 @@
status = "okay";
};
&cru {
assigned-clocks =
<&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>,
<&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>,
<&cru PLL_HPLL>, <&cru ARMCLK>,
<&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>,
<&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>,
<&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>,
<&cru HCLK_PDCORE_NIU>;
assigned-clock-rates =
<32768>, <1188000000>,
<100000000>, <491520000>,
<1400000000>, <600000000>,
<500000000>, <200000000>,
<100000000>, <300000000>,
<200000000>, <150000000>,
<200000000>;
};
&csi_dphy0 {
status = "okay";

19
arch/arm/boot/dts/rv1126-evb-uvc.dtsi
View File

@@ -3,6 +3,25 @@
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
&cru {
assigned-clocks =
<&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>,
<&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>,
<&cru PLL_HPLL>, <&cru ARMCLK>,
<&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>,
<&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>,
<&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>,
<&cru HCLK_PDCORE_NIU>;
assigned-clock-rates =
<32768>, <1188000000>,
<100000000>, <491520000>,
<1400000000>, <600000000>,
<500000000>, <200000000>,
<100000000>, <300000000>,
<200000000>, <150000000>,
<200000000>;
};
&i2s0_8ch {
clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>,
<&cru MCLK_I2S0_TX_DIV>, <&cru MCLK_I2S0_RX_DIV>,