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ARM: dts: rockchip: rv1106-ipc: add coherent_pool=0 to bootargs

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Signed-off-by: Zhichao Yu <zhichao.yu@rock-chips.com>
Change-Id: I451f5b220e5395a7af78cdc4989e086fc977108e
This commit is contained in:
Zhichao Yu
2022-05-13 10:28:10 +08:00
committed by Tao Huang
parent bfb97da050
commit adc69b3cef
1 changed files with 1 additions and 1 deletions
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2
arch/arm/boot/dts/rv1106-ipc.dtsi
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@@ -6,7 +6,7 @@
/ {
chosen {
bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyFIQ0 rootwait snd_soc_core.prealloc_buffer_size_kbytes=16";
bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyFIQ0 rootwait snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0";
};
acodec_sound: acodec-sound {