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drm/bridge: synopsys: dw-hdmi-qp: Fix PKTSCHED register access error
ACR located at Packet Scheduler which belongs to VIDQPCLK domain. So, the related clk should be enabled before register access. Actually, There are three CLK domain (AUDCLK, VIDQPCLK, LINKQPCLK) related to Audio. So, do check clk status before config audio. Maybe the better way should be spliting hdmi regmap into several parts which managed by related clk domain in future. e.g. devm_regmap_init_mmio_clk(dev, "aud", regs, AUD_REGBANK); devm_regmap_init_mmio_clk(dev, "vidqp", regs, VIDQP_REGBANK); devm_regmap_init_mmio_clk(dev, "linkqp", regs, LINKQP_REGBANK); ... Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: Ib497d92a73d99d9f38c4617f615f02c705b82ae7
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@@ -42,6 +42,13 @@ static inline void hdmi_mod(struct dw_hdmi_qp_i2s_audio_data *audio,
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return audio->mod(hdmi, data, mask, reg);
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}
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static inline bool is_dw_hdmi_qp_clk_off(struct dw_hdmi_qp_i2s_audio_data *audio)
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{
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u32 sta = hdmi_read(audio, CMU_STATUS);
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return (sta & (AUDCLK_OFF | LINKQPCLK_OFF | VIDQPCLK_OFF));
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}
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static int dw_hdmi_qp_i2s_hw_params(struct device *dev, void *data,
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struct hdmi_codec_daifmt *fmt,
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struct hdmi_codec_params *hparms)
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@@ -50,6 +57,9 @@ static int dw_hdmi_qp_i2s_hw_params(struct device *dev, void *data,
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struct dw_hdmi_qp *hdmi = audio->hdmi;
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u32 conf0 = 0;
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if (is_dw_hdmi_qp_clk_off(audio))
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return 0;
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if (fmt->bit_clk_master | fmt->frame_clk_master) {
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dev_err(dev, "unsupported clock settings\n");
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return -EINVAL;
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@@ -131,6 +141,9 @@ static int dw_hdmi_qp_i2s_audio_startup(struct device *dev, void *data)
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struct dw_hdmi_qp_i2s_audio_data *audio = data;
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struct dw_hdmi_qp *hdmi = audio->hdmi;
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if (is_dw_hdmi_qp_clk_off(audio))
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return 0;
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dw_hdmi_qp_audio_enable(hdmi);
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return 0;
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@@ -141,6 +154,9 @@ static void dw_hdmi_qp_i2s_audio_shutdown(struct device *dev, void *data)
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struct dw_hdmi_qp_i2s_audio_data *audio = data;
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struct dw_hdmi_qp *hdmi = audio->hdmi;
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if (is_dw_hdmi_qp_clk_off(audio))
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return;
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dw_hdmi_qp_audio_disable(hdmi);
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}
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@@ -37,6 +37,11 @@
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#define CMU_CONFIG2 0xa8
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#define CMU_CONFIG3 0xac
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#define CMU_STATUS 0xb0
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#define EARC_BPCLK_OFF BIT(9)
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#define AUDCLK_OFF BIT(7)
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#define LINKQPCLK_OFF BIT(5)
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#define VIDQPCLK_OFF BIT(3)
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#define IPI_CLK_OFF BIT(1)
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#define CMU_IPI_CLK_FREQ 0xb4
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#define CMU_VIDQPCLK_FREQ 0xb8
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#define CMU_LINKQPCLK_FREQ 0xbc
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