shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 19:30:30 +09:00
Code Issues Packages Projects Releases Wiki Activity

drm/rockchip: vop2: remove the clk limit for dp interfce

Browse Source 
When a video port just connect to dp and without hdmi, it still
can use hdmi phy pll as clk source if the pixel clk more than
600MHz.

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I975a0faaad867361c0888b795e9369ca1381634f
This commit is contained in:
Zhang Yubing
2022-05-17 10:50:44 +08:00
committed by Tao Huang
parent 600290f3f6
commit af0532f8a6
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -3670,7 +3670,7 @@ static int vop2_clk_set_parent_extend(struct vop2_video_port *vp,
hdmi1_phy_pll->vp_mask |= BIT(vp->id);
} else if (output_if_is_dp(vcstate->output_if)) {
if (adjusted_mode->crtc_clock > VOP2_MAX_DCLK_RATE || vp->id == 2) {
if (vp->id == 2) {
vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
return 0;
}