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arm64: dts: rockchip: rk3568: support clk_32k_ioe output 32k

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add xin32k dts node.
assigned-clock-parents for clk_32k_ioe.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I63500026e32b4dfe5debe3a2aa79f111e42a5fbc
This commit is contained in:
Elaine Zhang
2020-11-18 09:51:59 +08:00
committed by Tao Huang
parent 0cd2eda71e
commit afba90dde0
2 changed files with 26 additions and 6 deletions
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19
arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
View File

@@ -253,13 +253,20 @@
};
clk32k {
/omit-if-no-ref/
clk32k_pins: clk32k-pins {
clkin_32k: clkin-32k {
rockchip,pins =
<0 RK_PB0 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
clk32k_out0: clk32k-out0 {
rockchip,pins =
<0 RK_PB0 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
clk32k_out1: clk32k-out1 {
rockchip,pins =
/* clk32k_in */
<0 RK_PB0 1 &pcfg_pull_none>,
/* clk32k_out0 */
<0 RK_PB0 2 &pcfg_pull_none>,
/* clk32k_out1 */
<2 RK_PC6 1 &pcfg_pull_none>;
};
};

13
arch/arm64/boot/dts/rockchip/rk3568.dtsi
View File

@@ -205,6 +205,15 @@
clock-output-names = "xin24m";
};
xin32k: xin32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "xin32k";
#clock-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&clk32k_out0>;
};
sata0: sata@fc000000 {
compatible = "snps,dwc-ahci";
reg = <0 0xfc000000 0 0x1000>;
@@ -546,8 +555,12 @@
compatible = "rockchip,rk3568-pmucru";
reg = <0x0 0xfdd00000 0x0 0x1000>;
rockchip,grf = <&grf>;
rockchip,pmugrf = <&pmugrf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&pmucru SCLK_32K_IOE>;
assigned-clock-parents = <&pmucru CLK_RTC_32K>;
};
cru: clock-controller@fdd20000 {