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clk: rockchip: rk3288: Add ids for pclk_vip_in and pclk_vip

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Change-Id: Id7c4b9a69ca22ae5eaee75929adb5ec0c1f0165c
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Finley Xiao
2017-11-27 15:09:07 +08:00
committed by Tao Huang
parent cc03ee8220
commit b1b915251b
2 changed files with 4 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3288.c
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@@ -799,8 +799,8 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
* Other ungrouped clocks.
*/
GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS),
GATE(PCLK_VIP_IN, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
INVERTER(PCLK_VIP, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS),
GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
};

2
include/dt-bindings/clock/rk3288-cru.h
View File

@@ -174,6 +174,8 @@
#define PCLK_EFUSE256 369
#define PCLK_EFUSE1024 370
#define PCLK_ISP_IN 371
#define PCLK_VIP 372
#define PCLK_VIP_IN 373
/* hclk gates */
#define HCLK_GPS 448