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clk: rockchip: rk3368: add aclk_cci_pre ID

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Change-Id: I855e79023a9e244c2db37af88a075a4ef4c36aec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2017-04-07 17:35:28 +08:00
committed by Tao Huang
parent e7ebb13742
commit b1d64bdb31
2 changed files with 3 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3368.c
View File

@@ -321,8 +321,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
RK3368_CLKSEL_CON(4), 8, 5, DFLAGS,
RK3368_CLKGATE_CON(0), 13, GFLAGS),
COMPOSITE(0, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 7, DFLAGS,
COMPOSITE(ACLK_CCI_PRE, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(0), 12, GFLAGS),
GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),

1
include/dt-bindings/clock/rk3368-cru.h
View File

@@ -101,6 +101,7 @@
#define ACLK_VIDEO 208
#define ACLK_BUS 209
#define ACLK_PERI 210
#define ACLK_CCI_PRE 211
/* pclk gates */
#define PCLK_GPIO0 320