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nvme-pci: add NVME_QUIRK_LIMIT_IOQD32 to fix Phison E15 NVMe controller

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Phison E15 NVMe controller is known to be broken when doing a high loading
test. Limit io queue depth to 32 is suggested by vendor.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ie2a89197311a6a7b59281ff12caf545ae0ab37bf
This commit is contained in:
Shawn Lin
2023-06-26 15:01:20 +08:00
committed by Tao Huang
parent 1dd504da41
commit b20870d869
2 changed files with 10 additions and 0 deletions
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5
drivers/nvme/host/nvme.h
View File

@@ -155,6 +155,11 @@ enum nvme_quirks {
* Reports garbage in the namespace identifiers (eui64, nguid, uuid).
*/
NVME_QUIRK_BOGUS_NID = (1 << 18),
/*
* Limit io queue depth to 32
*/
NVME_QUIRK_LIMIT_IOQD32 = (1 << 31),
};
/*

5
drivers/nvme/host/pci.c
View File

@@ -2394,6 +2394,9 @@ static int nvme_pci_enable(struct nvme_dev *dev)
dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
if (dev->ctrl.quirks & NVME_QUIRK_LIMIT_IOQD32)
io_queue_depth = 32;
dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
io_queue_depth);
dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
@@ -3236,6 +3239,8 @@ static const struct pci_device_id nvme_id_table[] = {
.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
NVME_QUIRK_DISABLE_WRITE_ZEROES|
NVME_QUIRK_IGNORE_DEV_SUBNQN, },
{ PCI_DEVICE(0x1987, 0x5013), /* Phison E13 */
.driver_data = NVME_QUIRK_LIMIT_IOQD32},
{ PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
NVME_QUIRK_BOGUS_NID, },