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ODROID-XU4: arm: dts: exynos: enable per cpu thermal trips with irq-mode for Odroid HC1
Change-Id: I7e03be0fb60cd8948fa7bbde91789130b944a3b4 Signed-off-by: memeka <mihailescu2m@gmail.com>
This commit is contained in:
memeka
84
arch/arm/boot/dts/exynos5422-odroidhc1-trip-points.dtsi
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84
arch/arm/boot/dts/exynos5422-odroidhc1-trip-points.dtsi
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@@ -0,0 +1,84 @@
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/*
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* Device tree sources for default OdroidXU3/Exynos5422 thermal zone definition
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*
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* Copyright (c) 2015 Lukasz Majewski <l.majewski@samsung.com>
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* Anand Moon <linux.amoon@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#define _TOKENPASTE(x, y) x ## y
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#define TOKENPASTE(x, y) _TOKENPASTE(x, y)
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#define UNIQIFY(label) TOKENPASTE(label, CPU_THERMAL_ZONE_NUM)
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trips {
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UNIQIFY(cpu_alert0): cpu-alert-0 {
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temperature = <80000>; /* millicelsius */
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hysteresis = <2500>; /* millicelsius */
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type = "passive";
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irq-mode;
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};
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UNIQIFY(cpu_alert1): cpu-alert-1 {
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temperature = <85000>; /* millicelsius */
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hysteresis = <2500>; /* millicelsius */
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type = "passive";
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irq-mode;
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};
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UNIQIFY(cpu_alert2): cpu-alert-2 {
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temperature = <90000>; /* millicelsius */
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hysteresis = <2500>; /* millicelsius */
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type = "passive";
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irq-mode;
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};
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UNIQIFY(cpu_criti0): cpu-crit-0 {
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temperature = <120000>; /* millicelsius */
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hysteresis = <0>; /* millicelsius */
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type = "critical";
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irq-mode;
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};
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};
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cooling-maps {
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/*
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* When reaching cpu_alert0, reduce A15 cores by 4 steps.
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* The top frequency causes high thermals on multithreaded workloads
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* so better performance is gained by managing it out early.
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*/
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map0 {
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trip = <&UNIQIFY(cpu_alert0)>;
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cooling-device = <&cpu4 0 4>,
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<&cpu5 0 4>,
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<&cpu6 0 4>,
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<&cpu7 0 4>;
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};
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/*
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* When reaching cpu_alert1, reduce A15 cores by 4 more steps
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* to further manage the performance level while keeping
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* thermals under control.
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*/
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map1 {
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trip = <&UNIQIFY(cpu_alert1)>;
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cooling-device = <&cpu4 5 8>,
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<&cpu5 5 8>,
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<&cpu6 5 8>,
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<&cpu7 5 8>;
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};
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/*
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* When reaching cpu_alert2, reduce all CPUs to ensure thermal
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* safety. A7 cores don't produce much thermal load so they are
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* reduced less to optimise performance.
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*/
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map2 {
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trip = <&UNIQIFY(cpu_alert2)>;
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cooling-device = <&cpu0 0 4>,
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<&cpu1 0 4>,
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<&cpu2 0 4>,
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<&cpu3 0 4>,
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<&cpu4 9 12>,
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<&cpu5 9 12>,
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<&cpu6 9 12>,
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<&cpu7 9 12>;
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};
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};
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@@ -30,190 +30,27 @@
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thermal-zones {
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cpu0_thermal: cpu0-thermal {
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thermal-sensors = <&tmu_cpu0 0>;
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trips {
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cpu0_alert0: cpu-alert-0 {
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temperature = <70000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "active";
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};
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cpu0_alert1: cpu-alert-1 {
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temperature = <85000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "active";
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};
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cpu0_crit0: cpu-crit-0 {
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temperature = <120000>; /* millicelsius */
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hysteresis = <0>; /* millicelsius */
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type = "critical";
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};
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};
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cooling-maps {
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/*
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* When reaching cpu0_alert0, reduce CPU
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* by 2 steps. On Exynos5422/5800 that would
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* be: 1600 MHz and 1100 MHz.
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*/
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map0 {
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trip = <&cpu0_alert0>;
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cooling-device = <&cpu0 0 2>,
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<&cpu1 0 2>,
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<&cpu2 0 2>,
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<&cpu3 0 2>,
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<&cpu4 0 2>,
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<&cpu5 0 2>,
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<&cpu6 0 2>,
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<&cpu7 0 2>;
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};
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/*
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* When reaching cpu0_alert1, reduce CPU
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* further, down to 600 MHz (12 steps for big,
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* 7 steps for LITTLE).
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*/
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map1 {
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trip = <&cpu0_alert1>;
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cooling-device = <&cpu0 3 7>,
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<&cpu1 3 7>,
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<&cpu2 3 7>,
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<&cpu3 3 7>,
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<&cpu4 3 12>,
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<&cpu5 3 12>,
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<&cpu6 3 12>,
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<&cpu7 3 12>;
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};
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};
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#define CPU_THERMAL_ZONE_NUM 0
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#include "exynos5422-odroidhc1-trip-points.dtsi"
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#undef CPU_THERMAL_ZONE_NUM
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};
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cpu1_thermal: cpu1-thermal {
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thermal-sensors = <&tmu_cpu1 0>;
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trips {
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cpu1_alert0: cpu-alert-0 {
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temperature = <70000>;
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hysteresis = <10000>;
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type = "active";
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};
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cpu1_alert1: cpu-alert-1 {
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temperature = <85000>;
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hysteresis = <10000>;
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type = "active";
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};
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cpu1_crit0: cpu-crit-0 {
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temperature = <120000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu1_alert0>;
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cooling-device = <&cpu0 0 2>,
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<&cpu1 0 2>,
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<&cpu2 0 2>,
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<&cpu3 0 2>,
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<&cpu4 0 2>,
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<&cpu5 0 2>,
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<&cpu6 0 2>,
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<&cpu7 0 2>;
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};
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map1 {
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trip = <&cpu1_alert1>;
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cooling-device = <&cpu0 3 7>,
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<&cpu1 3 7>,
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<&cpu2 3 7>,
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<&cpu3 3 7>,
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<&cpu4 3 12>,
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<&cpu5 3 12>,
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<&cpu6 3 12>,
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<&cpu7 3 12>;
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};
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};
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#define CPU_THERMAL_ZONE_NUM 1
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#include "exynos5422-odroidhc1-trip-points.dtsi"
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#undef CPU_THERMAL_ZONE_NUM
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};
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cpu2_thermal: cpu2-thermal {
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thermal-sensors = <&tmu_cpu2 0>;
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trips {
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cpu2_alert0: cpu-alert-0 {
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temperature = <70000>;
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hysteresis = <10000>;
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type = "active";
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};
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cpu2_alert1: cpu-alert-1 {
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temperature = <85000>;
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hysteresis = <10000>;
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type = "active";
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};
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cpu2_crit0: cpu-crit-0 {
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temperature = <120000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu2_alert0>;
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cooling-device = <&cpu0 0 2>,
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<&cpu1 0 2>,
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<&cpu2 0 2>,
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<&cpu3 0 2>,
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<&cpu4 0 2>,
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<&cpu5 0 2>,
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<&cpu6 0 2>,
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<&cpu7 0 2>;
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};
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map1 {
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trip = <&cpu2_alert1>;
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cooling-device = <&cpu0 3 7>,
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<&cpu1 3 7>,
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<&cpu2 3 7>,
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<&cpu3 3 7>,
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<&cpu4 3 12>,
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<&cpu5 3 12>,
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<&cpu6 3 12>,
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<&cpu7 3 12>;
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};
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};
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#define CPU_THERMAL_ZONE_NUM 2
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#include "exynos5422-odroidhc1-trip-points.dtsi"
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#undef CPU_THERMAL_ZONE_NUM
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};
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cpu3_thermal: cpu3-thermal {
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thermal-sensors = <&tmu_cpu3 0>;
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trips {
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cpu3_alert0: cpu-alert-0 {
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temperature = <70000>;
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hysteresis = <10000>;
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type = "active";
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};
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cpu3_alert1: cpu-alert-1 {
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temperature = <85000>;
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hysteresis = <10000>;
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type = "active";
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};
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cpu3_crit0: cpu-crit-0 {
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temperature = <120000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu3_alert0>;
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cooling-device = <&cpu0 0 2>,
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<&cpu1 0 2>,
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<&cpu2 0 2>,
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<&cpu3 0 2>,
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<&cpu4 0 2>,
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<&cpu5 0 2>,
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<&cpu6 0 2>,
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<&cpu7 0 2>;
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};
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map1 {
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trip = <&cpu3_alert1>;
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cooling-device = <&cpu0 3 7>,
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<&cpu1 3 7>,
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<&cpu2 3 7>,
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<&cpu3 3 7>,
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<&cpu4 3 12>,
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<&cpu5 3 12>,
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<&cpu6 3 12>,
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<&cpu7 3 12>;
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};
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};
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#define CPU_THERMAL_ZONE_NUM 3
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#include "exynos5422-odroidhc1-trip-points.dtsi"
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#undef CPU_THERMAL_ZONE_NUM
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};
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};
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