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ARM: dts: rockchip: Update and clean up display nodes for rk3126/rk3128/px3se boards

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Change-Id: Ia9f5cf9db93e14e5539b2f0c91470c62b52a2b3d
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2018-12-13 20:12:00 +08:00
committed by Tao Huang
parent a11d7cbb6d
commit b5aaea950e
3 changed files with 8 additions and 72 deletions
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7
arch/arm/boot/dts/px3se-evb.dts
View File

@@ -262,7 +262,7 @@
status = "okay";
};
lvds-panel {
panel {
compatible = "samsung,lsl070nl01", "simple-panel";
power-supply = <&vcc33_lcd>;
backlight = <&backlight>;
@@ -270,10 +270,11 @@
rockchip,data-mapping = "vesa";
rockchip,data-width = <24>;
rockchip,output = "lvds";
status = "okay";
display-timings {
timing {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <48000000>;
hactive = <1024>;
vactive = <600>;

12
arch/arm/boot/dts/rk3126-bnd-d708.dtsi
View File

@@ -237,6 +237,10 @@
};
};
&route_dsi {
status = "okay";
};
&dmc {
center-supply = <&vdd_log>;
};
@@ -513,10 +517,6 @@
status = "okay";
};
&mipi_dphy {
status = "okay";
};
&nandc {
status = "okay";
};
@@ -579,10 +579,6 @@
status = "okay";
};
&route_dsi {
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vccadc_ref>;

61
arch/arm/boot/dts/rk3128-fireprime.dts
View File

@@ -61,15 +61,6 @@
status = "okay";
};
lvds_panel: lvds-panel {
status = "disabled";
ports {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
};
};
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
@@ -127,15 +118,6 @@
cpu-supply = <&vdd_arm>;
};
&display_subsystem {
status = "okay";
route {
route_lvds: route-lvds {
status = "disabled";
};
};
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
@@ -358,50 +340,7 @@
};
};
&lvds {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&lcdc_lcdc>;
ports {
lvds_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
lvds_out_panel: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
&pinctrl {
lcdc {
lcdc_lcdc: lcdc-lcdc {
rockchip,pins =
/* depend on the hardware */
<2 RK_PB0 1 &pcfg_pull_none>, /* DCLK */
/* <2 RK_PB1 1 &pcfg_pull_none>, /* HSYNC */
/* <2 RK_PB2 1 &pcfg_pull_none>, /* VSYNC */
<2 RK_PB3 1 &pcfg_pull_none>, /* DEN */
<2 RK_PB4 1 &pcfg_pull_none>, /* DATA10 */
<2 RK_PB5 1 &pcfg_pull_none>, /* DATA11 */
<2 RK_PB6 1 &pcfg_pull_none>, /* DATA12 */
<2 RK_PB7 1 &pcfg_pull_none>, /* DATA13 */
<2 RK_PC0 1 &pcfg_pull_none>, /* DATA14 */
<2 RK_PC1 1 &pcfg_pull_none>, /* DATA15 */
<2 RK_PC2 1 &pcfg_pull_none>, /* DATA16 */
<2 RK_PC3 1 &pcfg_pull_none>; /* DATA17 */
/* <2 RK_PC4 1 &pcfg_pull_none>, /* DATA18 */
/* <2 RK_PC5 1 &pcfg_pull_none>, /* DATA19 */
/* <2 RK_PC6 1 &pcfg_pull_none>, /* DATA20 */
/* <2 RK_PC7 1 &pcfg_pull_none>, /* DATA21 */
/* <2 RK_PD0 1 &pcfg_pull_none>, /* DATA22 */
/* <2 RK_PD1 1 &pcfg_pull_none>; /* DATA23 */
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <RK_GPIO3 22 RK_FUNC_GPIO &pcfg_pull_default>;