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ANDROID: arm64: Annotate icache_inval_pou as position-independent

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In preparation for re-using icache_inval_pou from the EL2 nVHE
hypervisor, annotate it as position-independent.

Signed-off-by: Quentin Perret <qperret@google.com>
Bug: 209580772
Change-Id: I66fbf42239a891bfd149c79bf77379fea124793e
Signed-off-by: Will Deacon <willdeacon@google.com>
This commit is contained in:
Quentin Perret
2021-11-30 13:47:02 +00:00
committed by Will Deacon
parent 4cd08ce604
commit b651d43f2a
1 changed files with 2 additions and 2 deletions
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4
arch/arm64/mm/cache.S
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@@ -88,7 +88,7 @@ SYM_FUNC_END(caches_clean_inval_user_pou)
* - start - virtual start address of region
* - end - virtual end address of region
*/
SYM_FUNC_START(icache_inval_pou)
SYM_FUNC_START_PI(icache_inval_pou)
alternative_if ARM64_HAS_CACHE_DIC
isb
ret
@@ -96,7 +96,7 @@ alternative_else_nop_endif
invalidate_icache_by_line x0, x1, x2, x3
ret
SYM_FUNC_END(icache_inval_pou)
SYM_FUNC_END_PI(icache_inval_pou)
/*
* dcache_clean_inval_poc(start, end)