shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 20:07:46 +09:00
Code Issues Packages Projects Releases Wiki Activity

media: hdmitx: Update hdmi hpll generation for low pixel clock

Browse Source 
Change-Id: I83bd8688379f7e70354013c5f1a02c6995beed31
This commit is contained in:
Joy Cho
2020-08-11 11:15:20 +09:00
parent e2a3ea38a1
commit b8262b15d8
2 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
View File

@@ -1110,8 +1110,8 @@ next:
p_enc[j].hpll_clk_out = (custom_timing->frac_freq * 10);
pr_info("[N2][%s] vic == HDMI_CUSTOMBUILT, frac_freq %d\n",
__func__, custom_timing->frac_freq);
/* check if hpll clk output is under (100*10)MHz */
if (p_enc[j].hpll_clk_out < 1000000) {
/* check if hpll clk output is under (140*10)MHz */
if (p_enc[j].hpll_clk_out < 1400000) {
p_enc[j].hpll_clk_out *= 4;
/* control od dividers */
p_enc[j].od1 = 4;

2
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
View File

@@ -331,7 +331,7 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
/* calculate "m" */
m1 = (clk * 0x3A) / 1422000;
m2 = (clk * 0xE1) / 5405400;
m = (m1 + m2)/2;
m = ((m1 + m2) / 2) + 1;
m &= 0xff;
m |= 0x3b000400;
hd_write_reg(P_HHI_HDMI_PLL_CNTL0, m);