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arm64: dts: rockchip: vehicle-display: set dsi resolution to 1920x720@60

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Change-Id: I3fef41dc1a70b43a43229b4f520692b6ce23b7f2
Signed-off-by: Luo Wei <lw@rock-chips.com>
This commit is contained in:
Luo Wei
2023-05-24 19:37:05 +08:00
committed by Tao Huang
parent 9e36581320
commit b9d6865a47
2 changed files with 54 additions and 4 deletions
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29
arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi
View File

@@ -215,7 +215,7 @@
display-timings {
native-mode = <&dsi2lvds0>;
dsi2lvds0: timing0 {
clock-frequency = <87000000>;
clock-frequency = <88208000>;
hactive = <1920>;
vactive = <720>;
hfront-porch = <32>;
@@ -251,7 +251,7 @@
display-timings {
native-mode = <&dsi2lvds1>;
dsi2lvds1: timing0 {
clock-frequency = <87000000>;
clock-frequency = <88208000>;
hactive = <1920>;
vactive = <720>;
hfront-porch = <32>;
@@ -1916,3 +1916,28 @@
rockchip,dp-lane-mux = <0 1 2 3>;
status = "okay";
};
&vop {
assigned-clocks = <&cru PLL_V0PLL>;
assigned-clock-rates = <1152000000>;
};
&vp0 {
assigned-clocks = <&cru DCLK_VOP0_SRC>;
assigned-clock-parents = <&cru PLL_V0PLL>;
};
&vp1 {
assigned-clocks = <&cru DCLK_VOP1_SRC>;
assigned-clock-parents = <&cru PLL_GPLL>;
};
&vp2 {
assigned-clocks = <&cru DCLK_VOP2_SRC>;
assigned-clock-parents = <&cru PLL_V0PLL>;
};
&vp3 {
assigned-clocks = <&cru DCLK_VOP3>;
assigned-clock-parents = <&cru PLL_V0PLL>;
};

29
arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display.dtsi
View File

@@ -215,7 +215,7 @@
display-timings {
native-mode = <&dsi2lvds0>;
dsi2lvds0: timing0 {
clock-frequency = <87000000>;
clock-frequency = <88208000>;
hactive = <1920>;
vactive = <720>;
hfront-porch = <32>;
@@ -251,7 +251,7 @@
display-timings {
native-mode = <&dsi2lvds1>;
dsi2lvds1: timing0 {
clock-frequency = <87000000>;
clock-frequency = <88208000>;
hactive = <1920>;
vactive = <720>;
hfront-porch = <32>;
@@ -1916,3 +1916,28 @@
rockchip,dp-lane-mux = <0 1 2 3>;
status = "okay";
};
&vop {
assigned-clocks = <&cru PLL_V0PLL>;
assigned-clock-rates = <1152000000>;
};
&vp0 {
assigned-clocks = <&cru DCLK_VOP0_SRC>;
assigned-clock-parents = <&cru PLL_V0PLL>;
};
&vp1 {
assigned-clocks = <&cru DCLK_VOP1_SRC>;
assigned-clock-parents = <&cru PLL_GPLL>;
};
&vp2 {
assigned-clocks = <&cru DCLK_VOP2_SRC>;
assigned-clock-parents = <&cru PLL_V0PLL>;
};
&vp3 {
assigned-clocks = <&cru DCLK_VOP3>;
assigned-clock-parents = <&cru PLL_V0PLL>;
};