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clk: rockchip: px30: Add support to set parent rate for vopl dclk

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Change-Id: I208471f938b1795273c4f33ac35b82d667a2b312
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2018-08-15 15:36:16 +08:00
committed by Tao Huang
parent c9ff227e0b
commit bb1005b17c
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-px30.c
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@@ -429,7 +429,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
&px30_dclk_vopb_fracmux, 0),
GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0,
COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
PX30_CLKSEL_CON(8), 11, 1, MFLAGS, 0, 8, DFLAGS,
PX30_CLKGATE_CON(2), 6, GFLAGS),
COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT,