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PD #98603(98115): Increase delay to 500us after reset PLL for lock error under high temperature

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Change-Id: If553552029e9ec7e6ec5a743a6076f692e2a9e0d
This commit is contained in:
tao.zeng
2014-10-14 05:54:01 +00:00
committed by Mauro Ribeiro
parent f641f64c51
commit bc4d6b2f94
1 changed files with 1 additions and 1 deletions
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2
arch/arm/mach-meson8b/clock.c
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@@ -1221,7 +1221,7 @@ SETPLL:
aml_write_reg32(P_HHI_SYS_PLL_CNTL, cpu_clk_cntl);
udelay_scaled(100, dst / 1000000, 24 /*clk_get_rate_xtal*/);
udelay_scaled(500, dst / 1000000, 24 /*clk_get_rate_xtal*/);
cntl = aml_read_reg32(P_HHI_SYS_PLL_CNTL);
if((cntl & (1<<31)) == 0){