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Merge 16477cdfef ("Merge tag 'asm-generic-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic") into android-mainline

Browse Source 
Steps on the way to 5.19-rc1

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I5950f1b0bda0f5ae96ec4d2c6004a19c011f0ac4
This commit is contained in:
Greg Kroah-Hartman
2022-06-05 14:23:19 +02:00
parent f16d89e083 16477cdfef
commit bc730a3cd5
1629 changed files with 64361 additions and 30015 deletions
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45
Documentation/devicetree/bindings/arm/arm,corstone1000.yaml Normal file
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@@ -0,0 +1,45 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Corstone1000 Device Tree Bindings
maintainers:
- Vishnu Banavath <vishnu.banavath@arm.com>
- Rui Miguel Silva <rui.silva@linaro.org>
description: |+
ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
processors.
Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
systems for M-Class (or other) processors for adding sensors, connectivity,
video, audio and machine learning at the edge System and security IPs to build
a secure SoC for a range of rich IoT applications, for example gateways, smart
cameras and embedded systems.
Integrated Secure Enclave providing hardware Root of Trust and supporting
seamless integration of the optional CryptoCell™-312 cryptographic
accelerator.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA
implementation of the Corstone1000 in the MPS3 prototyping board. See
ARM document DAI0550.
items:
- const: arm,corstone1000-mps3
- description: Corstone1000 FVP is the Fixed Virtual Platform
implementation of this system. See ARM ecosystems FVP's.
items:
- const: arm,corstone1000-fvp
additionalProperties: true
...

10
Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml
View File

@@ -64,6 +64,7 @@ properties:
- description: BCM47094 based boards
items:
- enum:
- asus,rt-ac88u
- dlink,dir-885l
- linksys,panamera
- luxul,abr-4500-v1
@@ -83,9 +84,14 @@ properties:
- brcm,bcm953012er
- brcm,bcm953012hr
- brcm,bcm953012k
- const: brcm,bcm53012
- const: brcm,bcm4708
- description: BCM53016 based boards
items:
- enum:
- meraki,mr32
- const: brcm,brcm53012
- const: brcm,brcm53016
- const: brcm,bcm53016
- const: brcm,bcm4708
additionalProperties: true

33
Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml Normal file
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@@ -0,0 +1,33 @@
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcmbca.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Broadband SoC device tree bindings
description:
Broadcom Broadband SoCs include family of high performance DSL/PON/Wireless
chips that can be used as home gateway, router and WLAN AP for residential,
enterprise and carrier applications.
maintainers:
- William Zhang <william.zhang@broadcom.com>
- Anand Gore <anand.gore@broadcom.com>
- Kursad Oney <kursad.oney@broadcom.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: BCM47622 based boards
items:
- enum:
- brcm,bcm947622
- const: brcm,bcm47622
- const: brcm,bcmbca
additionalProperties: true
...

119
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@@ -172,7 +172,7 @@ properties:
- karo,tx53 # Ka-Ro electronics TX53 module
- kiebackpeter,imx53-ddc # K+P imx53 DDC
- kiebackpeter,imx53-hsc # K+P imx53 HSC
- menlo,m53menlo
- menlo,m53menlo # i.MX53 Menlo board
- voipac,imx53-dmm-668 # Voipac i.MX53 X53-DMM-668
- const: fsl,imx53
@@ -192,6 +192,7 @@ properties:
items:
- enum:
- auvidea,h100 # Auvidea H100
- bosch,imx6q-acc # Bosch ACC i.MX6 Dual
- boundary,imx6q-nitrogen6_max
- boundary,imx6q-nitrogen6_som2
- boundary,imx6q-nitrogen6x
@@ -411,7 +412,6 @@ properties:
- technologic,imx6dl-ts4900
- technologic,imx6dl-ts7970
- toradex,colibri_imx6dl # Colibri iMX6 Modules
- toradex,colibri_imx6dl-v1_1 # Colibri iMX6 V1.1 Modules
- udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board
- vdl,lanmcu # Van der Laan LANMCU board
- wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board
@@ -488,17 +488,13 @@ properties:
- description: i.MX6DL Boards with Toradex Colibri iMX6DL/S Modules
items:
- enum:
- toradex,colibri_imx6dl-aster # Colibri iMX6DL/S Module on Aster Board
- toradex,colibri_imx6dl-eval-v3 # Colibri iMX6DL/S Module on Colibri Evaluation Board V3
- toradex,colibri_imx6dl-iris # Colibri iMX6DL/S Module on Iris Board
- toradex,colibri_imx6dl-iris-v2 # Colibri iMX6DL/S Module on Iris Board V2
- const: toradex,colibri_imx6dl # Colibri iMX6DL/S Module
- const: fsl,imx6dl
- description: i.MX6DL Boards with Toradex Colibri iMX6DL/S V1.1 Modules
items:
- enum:
- toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6DL/S V1.1 M. on Colibri Evaluation Board V3
- const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6DL/S V1.1 Module
- const: fsl,imx6dl
- description: i.MX6S DHCOM DRC02 Board
items:
- const: dh,imx6s-dhcom-drc02
@@ -613,6 +609,28 @@ properties:
- const: kontron,imx6ul-n6310-som
- const: fsl,imx6ul
- description: TQ-Systems TQMa6UL1 SoM on MBa6ULx board
items:
- enum:
- tq,imx6ul-tqma6ul1-mba6ulx
- const: tq,imx6ul-tqma6ul1 # MCIMX6G1
- const: fsl,imx6ul
- description: TQ-Systems TQMa6UL2 SoM on MBa6ULx board
items:
- enum:
- tq,imx6ul-tqma6ul2-mba6ulx
- const: tq,imx6ul-tqma6ul2 # MCIMX6G2
- const: fsl,imx6ul
- description: TQ-Systems TQMa6ULxL SoM on MBa6ULx[L] board
items:
- enum:
- tq,imx6ul-tqma6ul2l-mba6ulx # using LGA adapter
- tq,imx6ul-tqma6ul2l-mba6ulxl
- const: tq,imx6ul-tqma6ul2l # MCIMX6G2, LGA SoM variant
- const: fsl,imx6ul
- description: i.MX6ULL based Boards
items:
- enum:
@@ -640,26 +658,44 @@ properties:
- const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL
- const: fsl,imx6ull
- description: i.MX6ULL PHYTEC phyGATE-Tauri
items:
- enum:
- phytec,imx6ull-phygate-tauri-emmc
- phytec,imx6ull-phygate-tauri-nand
- const: phytec,imx6ull-phygate-tauri # PHYTEC phyGATE-Tauri with i.MX6 ULL
- const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL
- const: fsl,imx6ull
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules
items:
- enum:
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board
- toradex,colibri-imx6ull-aster # Colibri iMX6ULL Module on Aster Carrier Board
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board V3
- toradex,colibri-imx6ull-iris # Colibri iMX6ULL Module on Iris Carrier Board
- toradex,colibri-imx6ull-iris-v2 # Colibri iMX6ULL Module on Iris V2 Carrier Board
- const: toradex,colibri-imx6ull # Colibri iMX6ULL Module
- const: fsl,imx6dl
- const: fsl,imx6ull
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module
items:
- enum:
- toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1GB (eMMC) M. on Colibri Evaluation Board
- const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
- const: fsl,imx6dl
- toradex,colibri-imx6ull-emmc-aster # Colibri iMX6ULL 1G (eMMC) on Aster Carrier Board
- toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1G (eMMC) on Colibri Evaluation B. V3
- toradex,colibri-imx6ull-emmc-iris # Colibri iMX6ULL 1G (eMMC) on Iris Carrier Board
- toradex,colibri-imx6ull-emmc-iris-v2 # Colibri iMX6ULL 1G (eMMC) on Iris V2 Carrier Board
- const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
- const: fsl,imx6ull
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules
items:
- enum:
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Evaluation Board
- const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module
- const: fsl,imx6dl
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Eval. B. V3
- toradex,colibri-imx6ull-wifi-aster # Colibri iMX6ULL Wi-Fi / BT M. on Aster Carrier Board
- toradex,colibri-imx6ull-wifi-iris # Colibri iMX6ULL Wi-Fi / BT M. on Iris Carrier Board
- toradex,colibri-imx6ull-wifi-iris-v2 # Colibri iMX6ULL Wi-Fi / BT M. on Iris V2 Carrier Board
- const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module
- const: fsl,imx6ull
- description: Kontron N6411 S Board
items:
@@ -667,6 +703,21 @@ properties:
- const: kontron,imx6ull-n6411-som
- const: fsl,imx6ull
- description: TQ Systems TQMa6ULLx SoM on MBa6ULx board
items:
- enum:
- tq,imx6ull-tqma6ull2-mba6ulx
- const: tq,imx6ull-tqma6ull2 # MCIMX6Y2
- const: fsl,imx6ull
- description: TQ Systems TQMa6ULLxL SoM on MBa6ULx[L] board
items:
- enum:
- tq,imx6ull-tqma6ull2l-mba6ulx # using LGA adapter
- tq,imx6ull-tqma6ull2l-mba6ulxl
- const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant
- const: fsl,imx6ull
- description: i.MX6ULZ based Boards
items:
- enum:
@@ -707,6 +758,7 @@ properties:
- kam,imx7d-flex-concentrator-mfg # Kamstrup OMNIA Flex Concentrator in manufacturing mode
- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
- remarkable,imx7d-remarkable2 # i.MX7D ReMarkable 2 E-Ink Tablet
- storopack,imx7d-smegw01 # Storopack i.MX7D SMEGW01
- technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf
- technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit
- technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph
@@ -762,6 +814,7 @@ properties:
- enum:
- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
- boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board
- dmo,imx8mm-data-modul-edm-sbc # i.MX8MM eDM SBC
- emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
- fsl,imx8mm-evk # i.MX8MM EVK Board
@@ -772,6 +825,7 @@ properties:
- gw,imx8mm-gw7902 # i.MX8MM Gateworks Board
- gw,imx8mm-gw7903 # i.MX8MM Gateworks Board
- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
- menlo,mx8menlo # i.MX8MM Menlo board with Verdin SoM
- toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
- toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
- toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
@@ -834,6 +888,7 @@ properties:
- beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit
- bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2
- bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO
- fsl,imx8mn-ddr3l-evk # i.MX8MN DDR3L EVK Board
- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
- gw,imx8mn-gw7902 # i.MX8MM Gateworks Board
@@ -860,6 +915,17 @@ properties:
items:
- enum:
- fsl,imx8mp-evk # i.MX8MP EVK Board
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
- toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
- toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
- const: fsl,imx8mp
- description: Engicam i.Core MX8M Plus SoM based boards
items:
- enum:
- engicam,icore-mx8mp-edimm2.2 # i.MX8MP Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit
- const: engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM
- const: fsl,imx8mp
- description: PHYTEC phyCORE-i.MX8MP SoM based boards
@@ -868,6 +934,24 @@ properties:
- const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM
- const: fsl,imx8mp
- description: Toradex Boards with Verdin iMX8M Plus Modules
items:
- enum:
- toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia
- toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board
- const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT
- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
- const: fsl,imx8mp
- description: Toradex Boards with Verdin iMX8M Plus Wi-Fi / BT Modules
items:
- enum:
- toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia
- toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B.
- const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module
- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
- const: fsl,imx8mp
- description: i.MX8MQ based Boards
items:
- enum:
@@ -999,6 +1083,7 @@ properties:
- description: LS1021A based Boards
items:
- enum:
- fsl,ls1021a-iot
- fsl,ls1021a-moxa-uc-8410a
- fsl,ls1021a-qds
- fsl,ls1021a-tsn

5
Documentation/devicetree/bindings/arm/mediatek.yaml
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@@ -133,6 +133,11 @@ properties:
- const: mediatek,mt8183
- items:
- enum:
- mediatek,mt8192-evb
- const: mediatek,mt8192
- items:
- enum:
- mediatek,mt8195-demo
- mediatek,mt8195-evb
- const: mediatek,mt8195
- description: Google Burnet (HP Chromebook x360 11MK G3 EE)

32
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
View File

@@ -31,6 +31,7 @@ properties:
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8192-mmsys
- mediatek,mt8195-mmsys
- mediatek,mt8365-mmsys
- const: syscon
- items:
@@ -41,6 +42,30 @@ properties:
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier as defined by bindings
of the power controller specified by phandle. See
Documentation/devicetree/bindings/power/power-domain.yaml for details.
mboxes:
description:
Using mailbox to communicate with GCE, it should have this
property and list of phandle, mailbox specifiers. See
Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details.
$ref: /schemas/types.yaml#/definitions/phandle-array
mediatek,gce-client-reg:
description:
The register of client driver can be configured by gce with 4 arguments
defined in this property, such as phandle of gce, subsys id,
register offset and size.
Each subsys id is mapping to a base address of display function blocks
register which is defined in the gce header
include/dt-bindings/gce/<chip>-gce.h.
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
"#clock-cells":
const: 1
@@ -56,9 +81,16 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/power/mt8173-power.h>
#include <dt-bindings/gce/mt8173-gce.h>
mmsys: syscon@14000000 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0x14000000 0x1000>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
#clock-cells = <1>;
#reset-cells = <1>;
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
View File

@@ -26,6 +26,7 @@ properties:
- mediatek,mt8135-pericfg
- mediatek,mt8173-pericfg
- mediatek,mt8183-pericfg
- mediatek,mt8195-pericfg
- mediatek,mt8516-pericfg
- const: syscon
- items:

2
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
View File

@@ -23,6 +23,8 @@ properties:
enum:
- qcom,sc7180-llcc
- qcom,sc7280-llcc
- qcom,sc8180x-llcc
- qcom,sc8280xp-llcc
- qcom,sdm845-llcc
- qcom,sm6350-llcc
- qcom,sm8150-llcc

7
Documentation/devicetree/bindings/arm/omap/prcm.txt
View File

@@ -31,12 +31,17 @@ Required properties:
(base address and length)
- clocks: clocks for this module
- clockdomains: clockdomains for this module
- #clock-cells: From common clock binding
- clock-output-names: From common clock binding
Example:
cm: cm@48004000 {
cm: clock@48004000 {
compatible = "ti,omap3-cm";
reg = <0x48004000 0x4000>;
#clock-cells = <0>;
clock-output-names = "cm";
cm_clocks: clocks {
#address-cells = <1>;

21
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@@ -39,8 +39,11 @@ description: |
msm8994
msm8996
sa8155p
sa8540p
sc7180
sc7280
sc8180x
sc8280xp
sdm630
sdm632
sdm660
@@ -99,6 +102,7 @@ properties:
- items:
- enum:
- asus,sparrow
- lg,lenok
- const: qcom,apq8026
@@ -225,6 +229,18 @@ properties:
- google,senor
- const: qcom,sc7280
- items:
- enum:
- lenovo,flex-5g
- microsoft,surface-prox
- qcom,sc8180x-primus
- const: qcom,sc8180x
- items:
- enum:
- qcom,sc8280xp-qrd
- const: qcom,sc8280xp
- items:
- enum:
- fairphone,fp3
@@ -258,6 +274,11 @@ properties:
- qcom,sa8155p-adp
- const: qcom,sa8155p
- items:
- enum:
- qcom,sa8295p-adp
- const: qcom,sa8540p
- items:
- enum:
- fairphone,fp4

20
Documentation/devicetree/bindings/arm/renesas.yaml
View File

@@ -327,6 +327,18 @@ properties:
- const: renesas,spider-cpu
- const: renesas,r8a779f0
- description: R-Car V4H (R8A779G0)
items:
- enum:
- renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000)
- const: renesas,r8a779g0
- items:
- enum:
- renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000)
- const: renesas,white-hawk-cpu
- const: renesas,r8a779g0
- description: R-Car H3e (R8A779M0)
items:
- enum:
@@ -405,6 +417,8 @@ properties:
- description: RZ/G2UL (R9A07G043)
items:
- enum:
- renesas,smarc-evk # SMARC EVK
- enum:
- renesas,r9a07g043u11 # RZ/G2UL Type-1
- renesas,r9a07g043u12 # RZ/G2UL Type-2
@@ -430,6 +444,12 @@ properties:
- renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
- const: renesas,r9a07g054
- description: RZ/V2M (R9A09G011)
items:
- enum:
- renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
- const: renesas,r9a09g011
additionalProperties: true
...

23
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@@ -133,6 +133,11 @@ properties:
- firefly,roc-rk3399-pc-plus
- const: rockchip,rk3399
- description: Firefly Station M2
items:
- const: firefly,rk3566-roc-pc
- const: rockchip,rk3566
- description: FriendlyElec NanoPi R2S
items:
- const: friendlyarm,nanopi-r2s
@@ -502,9 +507,18 @@ properties:
- const: pine64,rockpro64
- const: rockchip,rk3399
- description: Pine64 Quartz64 Model A
- description: Pine64 Quartz64 Model A/B
items:
- const: pine64,quartz64-a
- enum:
- pine64,quartz64-a
- pine64,quartz64-b
- const: rockchip,rk3566
- description: Pine64 SoQuartz SoM
items:
- enum:
- pine64,soquartz-cm4io
- const: pine64,soquartz
- const: rockchip,rk3566
- description: Radxa Rock
@@ -545,6 +559,11 @@ properties:
- const: radxa,rock2-square
- const: rockchip,rk3288
- description: Radxa ROCK3 Model A
items:
- const: radxa,rock3a
- const: rockchip,rk3568
- description: Rikomagic MK808 v1
items:
- const: rikomagic,mk808

63
Documentation/devicetree/bindings/arm/stm32/stm32.yaml
View File

@@ -14,21 +14,6 @@ properties:
const: "/"
compatible:
oneOf:
- description: DH STM32MP1 SoM based Boards
items:
- enum:
- arrow,stm32mp157a-avenger96 # Avenger96
- dh,stm32mp153c-dhcom-drc02
- dh,stm32mp157c-dhcom-pdk2
- dh,stm32mp157c-dhcom-picoitx
- enum:
- dh,stm32mp153c-dhcom-som
- dh,stm32mp157a-dhcor-som
- dh,stm32mp157c-dhcom-som
- enum:
- st,stm32mp153
- st,stm32mp157
- description: emtrion STM32MP1 Argon based Boards
items:
- const: emtrion,stm32mp157c-emsbc-argon
@@ -65,6 +50,21 @@ properties:
- enum:
- st,stm32mp135f-dk
- const: st,stm32mp135
- description: ST STM32MP151 based Boards
items:
- enum:
- prt,prtt1a # Protonic PRTT1A
- prt,prtt1c # Protonic PRTT1C
- prt,prtt1s # Protonic PRTT1S
- const: st,stm32mp151
- description: DH STM32MP153 SoM based Boards
items:
- const: dh,stm32mp153c-dhcom-drc02
- const: dh,stm32mp153c-dhcom-som
- const: st,stm32mp153
- items:
- enum:
- shiratech,stm32mp157a-iot-box # IoT Box
@@ -72,12 +72,44 @@ properties:
- st,stm32mp157c-ed1
- st,stm32mp157a-dk1
- st,stm32mp157c-dk2
- const: st,stm32mp157
- items:
- const: st,stm32mp157a-dk1-scmi
- const: st,stm32mp157a-dk1
- const: st,stm32mp157
- items:
- const: st,stm32mp157c-dk2-scmi
- const: st,stm32mp157c-dk2
- const: st,stm32mp157
- items:
- const: st,stm32mp157c-ed1-scmi
- const: st,stm32mp157c-ed1
- const: st,stm32mp157
- items:
- const: st,stm32mp157c-ev1
- const: st,stm32mp157c-ed1
- const: st,stm32mp157
- items:
- const: st,stm32mp157c-ev1-scmi
- const: st,stm32mp157c-ev1
- const: st,stm32mp157c-ed1
- const: st,stm32mp157
- description: DH STM32MP1 SoM based Boards
items:
- enum:
- arrow,stm32mp157a-avenger96 # Avenger96
- const: dh,stm32mp157a-dhcor-som
- const: st,stm32mp157
- description: DH STM32MP1 SoM based Boards
items:
- enum:
- dh,stm32mp157c-dhcom-pdk2
- dh,stm32mp157c-dhcom-picoitx
- const: dh,stm32mp157c-dhcom-som
- const: st,stm32mp157
- description: Engicam i.Core STM32MP1 SoM based Boards
items:
@@ -103,6 +135,7 @@ properties:
- const: oct,stm32mp15xx-osd32
- enum:
- st,stm32mp157
- description: Odyssey STM32MP1 SoM based Boards
items:
- enum:

5
Documentation/devicetree/bindings/arm/sunxi.yaml
View File

@@ -391,6 +391,11 @@ properties:
- const: libretech,all-h5-cc-h5
- const: allwinner,sun50i-h5
- description: Lichee Pi Nano
items:
- const: licheepi,licheepi-nano
- const: allwinner,suniv-f1c100s
- description: Lichee Pi One
items:
- const: licheepi,licheepi-one

4
Documentation/devicetree/bindings/arm/syna.txt
View File

@@ -18,10 +18,6 @@ stable binding/ABI.
---------------------------------------------------------------
Boards with the Synaptics AS370 SoC shall have the following properties:
Required root node property:
compatible: "syna,as370"
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
shall have the following properties:

5
Documentation/devicetree/bindings/arm/ux500.yaml
View File

@@ -40,6 +40,11 @@ properties:
- const: samsung,codina
- const: st-ericsson,u8500
- description: Samsung Galaxy Exhibit (SGH-T599)
items:
- const: samsung,codina-tmo
- const: st-ericsson,u8500
- description: Samsung Galaxy Beam (GT-I8530)
items:
- const: samsung,gavini

147
Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml Normal file
View File

@@ -0,0 +1,147 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
maintainers:
- Michael Srba <Michael.Srba@seznam.cz>
description: |
This binding describes the dependencies (clocks, resets, power domains) which
need to be turned on in a sequence before communication over the AHB bus
becomes possible.
Additionally, the reg property is used to pass to the driver the location of
two sadly undocumented registers which need to be poked as part of the sequence.
The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart
controllers, a hexagon core, and a clock controller which provides clocks for
the above.
properties:
compatible:
items:
- const: qcom,msm8998-ssc-block-bus
- const: qcom,ssc-block-bus
reg:
description: |
Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1
registers
minItems: 2
maxItems: 2
reg-names:
items:
- const: mpm_sscaon_config0
- const: mpm_sscaon_config1
'#address-cells':
enum: [ 1, 2 ]
'#size-cells':
enum: [ 1, 2 ]
ranges: true
clocks:
minItems: 6
maxItems: 6
clock-names:
items:
- const: xo
- const: aggre2
- const: gcc_im_sleep
- const: aggre2_north
- const: ssc_xo
- const: ssc_ahbs
power-domains:
description: Power domain phandles for the ssc_cx and ssc_mx power domains
minItems: 2
maxItems: 2
power-domain-names:
items:
- const: ssc_cx
- const: ssc_mx
resets:
description: |
Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the
branch control register associated with the ssc_xo and ssc_ahbs clocks)
minItems: 2
maxItems: 2
reset-names:
items:
- const: ssc_reset
- const: ssc_bcr
qcom,halt-regs:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: describes how to locate the ssc AXI halt register
items:
- items:
- description: Phandle reference to a syscon representing TCSR
- description: offset for the ssc AXI halt register
required:
- compatible
- reg
- reg-names
- '#address-cells'
- '#size-cells'
- ranges
- clocks
- clock-names
- power-domains
- power-domain-names
- resets
- reset-names
- qcom,halt-regs
additionalProperties:
type: object
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
soc {
#address-cells = <1>;
#size-cells = <1>;
// devices under this node are physically located in the SSC block, connected to an ssc-internal bus;
ssc_ahb_slave: bus@10ac008 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus";
reg = <0x10ac008 0x4>, <0x10ac010 0x4>;
reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1";
clocks = <&xo>,
<&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
<&gcc GCC_IM_SLEEP>,
<&gcc AGGRE2_SNOC_NORTH_AXI>,
<&gcc SSC_XO>,
<&gcc SSC_CNOC_AHBS_CLK>;
clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs";
resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>;
reset-names = "ssc_reset", "ssc_bcr";
power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>;
power-domain-names = "ssc_cx", "ssc_mx";
qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;
};
};

172
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml Normal file
View File

@@ -0,0 +1,172 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core & Audio Clock Controller Binding for SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm LPASS core and audio clock control module which supports the
clocks and power domains on SC7280.
See also:
- dt-bindings/clock/qcom,lpasscorecc-sc7280.h
- dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
properties:
clocks: true
clock-names: true
compatible:
enum:
- qcom,sc7280-lpassaoncc
- qcom,sc7280-lpassaudiocc
- qcom,sc7280-lpasscorecc
- qcom,sc7280-lpasshm
power-domains:
maxItems: 1
'#clock-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: qcom,sc7280-lpassaudiocc
then:
properties:
clocks:
items:
- description: Board XO source
- description: LPASS_AON_CC_MAIN_RCG_CLK_SRC
clock-names:
items:
- const: bi_tcxo
- const: lpass_aon_cc_main_rcg_clk_src
- if:
properties:
compatible:
contains:
enum:
- qcom,sc7280-lpassaoncc
then:
properties:
clocks:
items:
- description: Board XO source
- description: Board XO active only source
- description: LPASS_AON_CC_MAIN_RCG_CLK_SRC
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: iface
- if:
properties:
compatible:
contains:
enum:
- qcom,sc7280-lpasshm
- qcom,sc7280-lpasscorecc
then:
properties:
clocks:
items:
- description: Board XO source
clock-names:
items:
- const: bi_tcxo
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
lpass_audiocc: clock-controller@3300000 {
compatible = "qcom,sc7280-lpassaudiocc";
reg = <0x3300000 0x30000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
lpass_hm: clock-controller@3c00000 {
compatible = "qcom,sc7280-lpasshm";
reg = <0x3c00000 0x28>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
#clock-cells = <1>;
#power-domain-cells = <1>;
};
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
lpasscore: clock-controller@3900000 {
compatible = "qcom,sc7280-lpasscorecc";
reg = <0x3900000 0x50000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
lpass_aon: clock-controller@3380000 {
compatible = "qcom,sc7280-lpassaoncc";
reg = <0x3380000 0x30000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&lpasscore LPASS_CORE_CC_CORE_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
#clock-cells = <1>;
#power-domain-cells = <1>;
};
...

24
Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt
View File

@@ -1,24 +0,0 @@
* Renesas H8/300 divider clock
Required Properties:
- compatible: Must be "renesas,h8300-div-clock"
- clocks: Reference to the parent clocks ("extal1" and "extal2")
- #clock-cells: Must be 1
- reg: Base address and length of the divide rate selector
- renesas,width: bit width of selector
Example
-------
cclk: cclk {
compatible = "renesas,h8300-div-clock";
clocks = <&xclk>;
#clock-cells = <0>;
reg = <0xfee01b 2>;
renesas,width = <2>;
};

23
Documentation/devicetree/bindings/clock/renesas,h8s2678-pll-clock.txt
View File

@@ -1,23 +0,0 @@
Renesas H8S2678 PLL clock
This device is Clock multiplyer
Required Properties:
- compatible: Must be "renesas,h8s2678-pll-clock"
- clocks: Reference to the parent clocks
- #clock-cells: Must be 0
- reg: Two rate selector (Multiply / Divide) register address
Example
-------
pllclk: pllclk {
compatible = "renesas,h8s2678-pll-clock";
clocks = <&xclk>;
#clock-cells = <0>;
reg = <0xfee03b 2>, <0xfee045 2>;
};

219
Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml Normal file
View File

@@ -0,0 +1,219 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos Auto v9 SoC clock controller
maintainers:
- Chanho Park <chanho61.park@samsung.com>
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>
description: |
Exynos Auto v9 clock controller is comprised of several CMU units, generating
clocks for different domains. Those CMU units are modeled as separate device
tree nodes, and might depend on each other. Root clocks in that clock tree are
two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
The external OSCCLK must be defined as fixed-rate clock in dts.
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
dividers; all other clocks of function blocks (other CMUs) are usually
derived from CMU_TOP.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All clocks available for usage
in clock consumer nodes are defined as preprocessor macros in
'include/dt-bindings/clock/samsung,exynosautov9.h' header.
properties:
compatible:
enum:
- samsung,exynosautov9-cmu-top
- samsung,exynosautov9-cmu-busmc
- samsung,exynosautov9-cmu-core
- samsung,exynosautov9-cmu-fsys2
- samsung,exynosautov9-cmu-peric0
- samsung,exynosautov9-cmu-peric1
- samsung,exynosautov9-cmu-peris
clocks:
minItems: 1
maxItems: 5
clock-names:
minItems: 1
maxItems: 5
"#clock-cells":
const: 1
reg:
maxItems: 1
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-top
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
clock-names:
items:
- const: oscclk
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-busmc
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_BUSMC bus clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_busmc_bus
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-core
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_CORE bus clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_core_bus
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-fsys2
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_FSYS2 bus clock (from CMU_TOP)
- description: UFS clock (from CMU_TOP)
- description: Ethernet clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_fsys2_bus
- const: dout_fsys2_clkcmu_ufs_embd
- const: dout_fsys2_clkcmu_ethernet
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-peric0
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_PERIC0 bus clock (from CMU_TOP)
- description: PERIC0 IP clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_peric0_bus
- const: dout_clkcmu_peric0_ip
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-peric1
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_PERIC1 bus clock (from CMU_TOP)
- description: PERIC1 IP clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_peric1_bus
- const: dout_clkcmu_peric1_ip
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-peris
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_PERIS bus clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_peris_bus
required:
- compatible
- "#clock-cells"
- clocks
- clock-names
- reg
additionalProperties: false
examples:
# Clock controller node for CMU_FSYS2
- |
#include <dt-bindings/clock/samsung,exynosautov9.h>
cmu_fsys2: clock-controller@17c00000 {
compatible = "samsung,exynosautov9-cmu-fsys2";
reg = <0x17c00000 0x8000>;
#clock-cells = <1>;
clocks = <&xtcxo>,
<&cmu_top DOUT_CLKCMU_FSYS2_BUS>,
<&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>,
<&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>;
clock-names = "oscclk",
"dout_clkcmu_fsys2_bus",
"dout_fsys2_clkcmu_ufs_embd",
"dout_fsys2_clkcmu_ethernet";
};
...

41
Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
View File

@@ -58,6 +58,8 @@ properties:
- st,stm32mp1-rcc-secure
- st,stm32mp1-rcc
- const: syscon
clocks: true
clock-names: true
reg:
maxItems: 1
@@ -68,14 +70,53 @@ required:
- compatible
- reg
if:
properties:
compatible:
contains:
enum:
- st,stm32mp1-rcc-secure
then:
properties:
clocks:
description: Specifies oscillators.
maxItems: 5
clock-names:
items:
- const: hse
- const: hsi
- const: csi
- const: lse
- const: lsi
required:
- clocks
- clock-names
else:
properties:
clocks:
description:
Specifies the external RX clock for ethernet MAC.
maxItems: 1
clock-names:
const: ETH_RX_CLK/ETH_REF_CLK
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/stm32mp1-clks.h>
rcc: rcc@50000000 {
compatible = "st,stm32mp1-rcc-secure", "syscon";
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_CSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>;
};
...

4
Documentation/devicetree/bindings/clock/ti-clkctrl.txt
View File

@@ -21,6 +21,7 @@ Required properties :
"ti,clkctrl-l4-per"
"ti,clkctrl-l4-secure"
"ti,clkctrl-l4-wkup"
- clock-output-names : from common clock binding
- #clock-cells : shall contain 2 with the first entry being the instance
offset from the clock domain base and the second being the
clock index
@@ -32,7 +33,8 @@ Example: Clock controller node on omap 4430:
l4per: cm@1400 {
cm_l4per@0 {
cm_l4per_clkctrl: clock@20 {
compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
compatible = "ti,clkctrl";
clock-output-names = "l4_per";
reg = <0x20 0x1b0>;
#clock-cells = <2>;
};

3
Documentation/devicetree/bindings/clock/ti/clockdomain.txt
View File

@@ -17,6 +17,9 @@ Required properties:
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of clocks within this domain
Optional properties:
- clock-output-names : from common clock binding.
Examples:
dss_clkdm: dss_clkdm {
compatible = "ti,clockdomain";

3
Documentation/devicetree/bindings/clock/ti/composite.txt
View File

@@ -27,6 +27,9 @@ Required properties:
- clocks : link phandles of component clocks
- #clock-cells : from common clock binding; shall be set to 0.
Optional properties:
- clock-output-names : from common clock binding.
Examples:
usb_l4_gate_ick: usb_l4_gate_ick {

1
Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt
View File

@@ -16,6 +16,7 @@ Required properties:
- clocks: parent clock.
Optional properties:
- clock-output-names : from common clock binding.
- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
see [2]
- reg: offset for the autoidle register of this clock, see [2]

1
Documentation/devicetree/bindings/clock/ti/gate.txt
View File

@@ -36,6 +36,7 @@ Required properties:
ti,clkdm-gate-clock type
Optional properties:
- clock-output-names : from common clock binding.
- ti,bit-shift : bit shift for programming the clock gate, invalid for
ti,clkdm-gate-clock type
- ti,set-bit-to-disable : inverts default gate programming. Setting the bit

1
Documentation/devicetree/bindings/clock/ti/interface.txt
View File

@@ -28,6 +28,7 @@ Required properties:
- reg : base address for the control register
Optional properties:
- clock-output-names : from common clock binding.
- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
Examples:

1
Documentation/devicetree/bindings/clock/ti/mux.txt
View File

@@ -42,6 +42,7 @@ Required properties:
- reg : register offset for register controlling adjustable mux
Optional properties:
- clock-output-names : from common clock binding.
- ti,bit-shift : number of bits to shift the bit-mask, defaults to
0 if not present
- ti,index-starts-at-one : valid input select programming starts at 1, not

8
Documentation/devicetree/bindings/dma/fsl-imx-dma.txt
View File

@@ -13,8 +13,10 @@ Required properties:
- #dma-cells : Has to be 1. imx-dma does not support anything else.
Optional properties:
- #dma-channels : Number of DMA channels supported. Should be 16.
- #dma-requests : Number of DMA requests supported.
- dma-channels : Number of DMA channels supported. Should be 16.
- #dma-channels : deprecated
- dma-requests : Number of DMA requests supported.
- #dma-requests : deprecated
Example:
@@ -23,7 +25,7 @@ Example:
reg = <0x10001000 0x1000>;
interrupts = <32 33>;
#dma-cells = <1>;
#dma-channels = <16>;
dma-channels = <16>;
};

3
Documentation/devicetree/bindings/firmware/qcom,scm.txt
View File

@@ -19,6 +19,7 @@ Required properties:
* "qcom,scm-msm8953"
* "qcom,scm-msm8960"
* "qcom,scm-msm8974"
* "qcom,scm-msm8976"
* "qcom,scm-msm8994"
* "qcom,scm-msm8996"
* "qcom,scm-msm8998"
@@ -37,7 +38,7 @@ Required properties:
* core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660" and
"qcom,scm-msm8960"
* core, iface and bus clocks required for "qcom,scm-apq8084",
"qcom,scm-msm8916", "qcom,scm-msm8953" and "qcom,scm-msm8974"
"qcom,scm-msm8916", "qcom,scm-msm8953", "qcom,scm-msm8974" and "qcom,scm-msm8976"
- clock-names: Must contain "core" for the core clock, "iface" for the interface
clock and "bus" for the bus clock per the requirements of the compatible.
- qcom,dload-mode: phandle to the TCSR hardware block and offset of the

13
Documentation/devicetree/bindings/h8300/cpu.txt
View File

@@ -1,13 +0,0 @@
* H8/300 CPU bindings
Required properties:
- compatible: Compatible property value should be "renesas,h8300".
- clock-frequency: Contains the clock frequency for CPU, in Hz.
Example:
cpu@0 {
compatible = "renesas,h8300";
clock-frequency = <20000000>;
};

8
Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml
View File

@@ -45,20 +45,20 @@ additionalProperties: false
examples:
# Example 1: apps bcm_voter on SDM845 SoC should be defined inside &apps_rsc node
# as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
# as defined in Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
- |
apps_bcm_voter: bcm_voter {
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
};
# Example 2: disp bcm_voter on SDM845 should be defined inside &disp_rsc node
# as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
# as defined in Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
- |
#include <dt-bindings/interconnect/qcom,icc.h>
disp_bcm_voter: bcm_voter {
disp_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
};

22
Documentation/devicetree/bindings/interrupt-controller/renesas,h8300h-intc.txt
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@@ -1,22 +0,0 @@
* H8/300H Interrupt controller
Required properties:
- compatible: has to be "renesas,h8300h-intc", "renesas,h8300-intc" as fallback.
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
interrupts.txt in this directory
- regs: Base address of interrupt controller registers.
Optional properties:
- any properties, listed in interrupts.txt, and any standard resource allocation
properties
Example:
h8intc: interrupt-controller@fee012 {
compatible = "renesas,h8300h-intc", "renesas,h8300-intc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0xfee012 7>;
};

22
Documentation/devicetree/bindings/interrupt-controller/renesas,h8s-intc.txt
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@@ -1,22 +0,0 @@
* H8S Interrupt controller
Required properties:
- compatible: has to be "renesas,h8s-intc", "renesas,h8300-intc" as fallback.
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
interrupts.txt in this directory
- regs: Base address of interrupt controller registers.
Optional properties:
- any properties, listed in interrupts.txt, and any standard resource allocation
properties
Example:
h8intc: interrupt-controller@fffe00 {
compatible = "renesas,h8s-intc", "renesas,h8300-intc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0xfffe00 24>;
};

52
Documentation/devicetree/bindings/iommu/apple,sart.yaml Normal file
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@@ -0,0 +1,52 @@
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/apple,sart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple SART DMA address filter
maintainers:
- Sven Peter <sven@svenpeter.dev>
description:
Apple SART is a simple address filter for DMA transactions. Regions of
physical memory must be added to the SART's allow list before any
DMA can target these. Unlike a proper IOMMU no remapping can be done and
special support in the consumer driver is required since not all DMA
transactions of a single device are subject to SART filtering.
SART1 has first been used since at least the A11 (iPhone 8 and iPhone X)
and allows 36 bit of physical address space and filter entries with sizes
up to 24 bit.
SART2, first seen in A14 and M1, allows 36 bit of physical address space
and filter entry size up to 36 bit.
SART3, first seen in M1 Pro/Max, extends both the address space and filter
entry size to 42 bit.
properties:
compatible:
enum:
- apple,t6000-sart
- apple,t8103-sart
reg:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
iommu@7bc50000 {
compatible = "apple,t8103-sart";
reg = <0x7bc50000 0x4000>;
};

80
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
View File

@@ -34,8 +34,12 @@ properties:
- nvidia,tegra234-mc
reg:
minItems: 1
maxItems: 3
minItems: 6
maxItems: 18
reg-names:
minItems: 6
maxItems: 18
interrupts:
items:
@@ -142,7 +146,18 @@ allOf:
then:
properties:
reg:
maxItems: 1
maxItems: 6
description: 5 memory controller channels and 1 for stream-id registers
reg-names:
maxItems: 6
items:
- const: sid
- const: broadcast
- const: ch0
- const: ch1
- const: ch2
- const: ch3
- if:
properties:
@@ -151,7 +166,30 @@ allOf:
then:
properties:
reg:
minItems: 3
minItems: 18
description: 17 memory controller channels and 1 for stream-id registers
reg-names:
minItems: 18
items:
- const: sid
- const: broadcast
- const: ch0
- const: ch1
- const: ch2
- const: ch3
- const: ch4
- const: ch5
- const: ch6
- const: ch7
- const: ch8
- const: ch9
- const: ch10
- const: ch11
- const: ch12
- const: ch13
- const: ch14
- const: ch15
- if:
properties:
@@ -160,13 +198,37 @@ allOf:
then:
properties:
reg:
minItems: 3
minItems: 18
description: 17 memory controller channels and 1 for stream-id registers
reg-names:
minItems: 18
items:
- const: sid
- const: broadcast
- const: ch0
- const: ch1
- const: ch2
- const: ch3
- const: ch4
- const: ch5
- const: ch6
- const: ch7
- const: ch8
- const: ch9
- const: ch10
- const: ch11
- const: ch12
- const: ch13
- const: ch14
- const: ch15
additionalProperties: false
required:
- compatible
- reg
- reg-names
- interrupts
- "#address-cells"
- "#size-cells"
@@ -182,7 +244,13 @@ examples:
memory-controller@2c00000 {
compatible = "nvidia,tegra186-mc";
reg = <0x0 0x02c00000 0x0 0xb0000>;
reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
<0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
<0x0 0x02c20000 0x0 0x10000>, /* MC0 */
<0x0 0x02c30000 0x0 0x10000>, /* MC1 */
<0x0 0x02c40000 0x0 0x10000>, /* MC2 */
<0x0 0x02c50000 0x0 0x10000>; /* MC3 */
reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;

35
Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.yaml
View File

@@ -1,35 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/renesas,h8300-bsc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: H8/300 bus controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
- Yoshinori Sato <ysato@users.sourceforge.jp>
properties:
compatible:
items:
- enum:
- renesas,h8300h-bsc
- renesas,h8s-bsc
- const: renesas,h8300-bsc
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
memory-controller@fee01e {
compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";
reg = <0xfee01e 8>;
};

6
Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml
View File

@@ -31,14 +31,20 @@ properties:
- renesas,r8a774b1-rpc-if # RZ/G2N
- renesas,r8a774c0-rpc-if # RZ/G2E
- renesas,r8a774e1-rpc-if # RZ/G2H
- renesas,r8a7795-rpc-if # R-Car H3
- renesas,r8a7796-rpc-if # R-Car M3-W
- renesas,r8a77961-rpc-if # R-Car M3-W+
- renesas,r8a77965-rpc-if # R-Car M3-N
- renesas,r8a77970-rpc-if # R-Car V3M
- renesas,r8a77980-rpc-if # R-Car V3H
- renesas,r8a77990-rpc-if # R-Car E3
- renesas,r8a77995-rpc-if # R-Car D3
- renesas,r8a779a0-rpc-if # R-Car V3U
- const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 or RZ/G2{E,H,M,N} device
- items:
- enum:
- renesas,r9a07g043-rpc-if # RZ/G2UL
- renesas,r9a07g044-rpc-if # RZ/G2{L,LC}
- renesas,r9a07g054-rpc-if # RZ/V2L
- const: renesas,rzg2l-rpc-if

1
Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml
View File

@@ -39,6 +39,7 @@ properties:
compatible:
items:
- enum:
- prt,prtt1c-wfm200 # Protonic PRTT1C Board
- silabs,brd4001a # WGM160P Evaluation Board
- silabs,brd8022a # WF200 Evaluation Board
- silabs,brd8023a # WFM200 Evaluation Board

111
Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml Normal file
View File

@@ -0,0 +1,111 @@
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvme/apple,nvme-ans.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple ANS NVM Express host controller
maintainers:
- Sven Peter <sven@svenpeter.dev>
properties:
compatible:
items:
- enum:
- apple,t8103-nvme-ans2
- apple,t6000-nvme-ans2
- const: apple,nvme-ans2
reg:
items:
- description: NVMe and NVMMU registers
- description: ANS2 co-processor control registers
reg-names:
items:
- const: nvme
- const: ans
resets:
maxItems: 1
power-domains:
# two domains for t8103, three for t6000
minItems: 2
items:
- description: power domain for the NVMe controller.
- description: power domain for the first PCIe bus connecting the NVMe
controller to the storage modules.
- description: optional power domain for the second PCIe bus
connecting the NVMe controller to the storage modules.
power-domain-names:
minItems: 2
items:
- const: ans
- const: apcie0
- const: apcie1
mboxes:
maxItems: 1
description: Mailbox of the ANS2 co-processor
interrupts:
maxItems: 1
apple,sart:
maxItems: 1
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Reference to the SART address filter.
The SART address filter is documented in iommu/apple,sart.yaml.
if:
properties:
compatible:
contains:
const: apple,t8103-nvme-ans2
then:
properties:
power-domains:
maxItems: 2
power-domain-names:
maxItems: 2
else:
properties:
power-domains:
minItems: 3
power-domain-names:
minItems: 3
required:
- compatible
- reg
- reg-names
- resets
- power-domains
- power-domain-names
- mboxes
- interrupts
- apple,sart
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
nvme@7bcc0000 {
compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2";
reg = <0x7bcc0000 0x40000>, <0x77400000 0x4000>;
reg-names = "nvme", "ans";
interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>;
mboxes = <&ans>;
apple,sart = <&sart>;
power-domains = <&ps_ans2>, <&ps_apcie_st>;
power-domain-names = "ans", "apcie0";
resets = <&ps_ans2>;
};

3
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
View File

@@ -27,12 +27,15 @@ properties:
- qcom,msm8998-rpmpd
- qcom,qcm2290-rpmpd
- qcom,qcs404-rpmpd
- qcom,sa8540p-rpmhpd
- qcom,sdm660-rpmpd
- qcom,sc7180-rpmhpd
- qcom,sc7280-rpmhpd
- qcom,sc8180x-rpmhpd
- qcom,sc8280xp-rpmhpd
- qcom,sdm845-rpmhpd
- qcom,sdx55-rpmhpd
- qcom,sdx65-rpmhpd
- qcom,sm6115-rpmpd
- qcom,sm6125-rpmpd
- qcom,sm6350-rpmhpd

1
Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
View File

@@ -44,6 +44,7 @@ properties:
- renesas,r8a77995-sysc # R-Car D3
- renesas,r8a779a0-sysc # R-Car V3U
- renesas,r8a779f0-sysc # R-Car S4-8
- renesas,r8a779g0-sysc # R-Car V4H
reg:
maxItems: 1

5
Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml
View File

@@ -12,7 +12,7 @@ description:
resides as a subnode of the SMD. As such, the SMD-RPM regulator requires
that the SMD and RPM nodes be present.
Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt for
Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml for
information pertaining to the SMD node.
Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
@@ -69,7 +69,8 @@ description:
l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22
maintainers:
- Kathiravan T <kathirav@codeaurora.org>
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
properties:
compatible:

2
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
View File

@@ -250,7 +250,7 @@ the memory regions used by the Hexagon firmware. Each sub-node must contain:
The Hexagon node may also have an subnode named either "smd-edge" or
"glink-edge" that describes the communication edge, channels and devices
related to the Hexagon. See ../soc/qcom/qcom,smd.txt and
related to the Hexagon. See ../soc/qcom/qcom,smd.yaml and
../soc/qcom/qcom,glink.txt for details on how to describe these.
= EXAMPLE

2
Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt
View File

@@ -111,7 +111,7 @@ and its resource dependencies. It is described by the following properties:
The wcnss node can also have an subnode named "smd-edge" that describes the SMD
edge, channels and devices related to the WCNSS.
See ../soc/qcom/qcom,smd.txt for details on how to describe the SMD edge.
See ../soc/qcom/qcom,smd.yaml for details on how to describe the SMD edge.
= EXAMPLE
The following example describes the resources needed to boot control the WCNSS,

47
Documentation/devicetree/bindings/reset/altr,rst-mgr.yaml Normal file
View File

@@ -0,0 +1,47 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/altr,rst-mgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera SOCFPGA Reset Manager
maintainers:
- Dinh Nguyen <dinguyen@altera.com>
properties:
compatible:
oneOf:
- description: Cyclone5/Arria5/Arria10
const: altr,rst-mgr
- description: Stratix10 ARM64 SoC
items:
- const: altr,stratix10-rst-mgr
- const: altr,rst-mgr
reg:
maxItems: 1
altr,modrst-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description: Offset of the first modrst register
'#reset-cells':
const: 1
required:
- compatible
- reg
- altr,modrst-offset
- '#reset-cells'
additionalProperties: false
examples:
- |
rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
altr,modrst-offset = <0x10>;
#reset-cells = <1>;
};

22
Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt
View File

@@ -1,22 +0,0 @@
* Amlogic audio memory arbiter controller
The Amlogic Audio ARB is a simple device which enables or
disables the access of Audio FIFOs to DDR on AXG based SoC.
Required properties:
- compatible: 'amlogic,meson-axg-audio-arb' or
'amlogic,meson-sm1-audio-arb'
- reg: physical base address of the controller and length of memory
mapped region.
- clocks: phandle to the fifo peripheral clock provided by the audio
clock controller.
- #reset-cells: must be 1.
Example on the A113 SoC:
arb: reset-controller@280 {
compatible = "amlogic,meson-axg-audio-arb";
reg = <0x0 0x280 0x0 0x4>;
#reset-cells = <1>;
clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
};

56
Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.yaml Normal file
View File

@@ -0,0 +1,56 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/amlogic,meson-axg-audio-arb.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic audio memory arbiter controller
maintainers:
- Jerome Brunet <jbrunet@baylibre.com>
description: The Amlogic Audio ARB is a simple device which enables or disables
the access of Audio FIFOs to DDR on AXG based SoC.
properties:
compatible:
enum:
- amlogic,meson-axg-audio-arb
- amlogic,meson-sm1-audio-arb
reg:
maxItems: 1
clocks:
maxItems: 1
description: |
phandle to the fifo peripheral clock provided by the audio clock
controller.
"#reset-cells":
const: 1
required:
- compatible
- reg
- clocks
- "#reset-cells"
additionalProperties: false
examples:
- |
// on the A113 SoC:
#include <dt-bindings/clock/axg-audio-clkc.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
arb: reset-controller@280 {
compatible = "amlogic,meson-axg-audio-arb";
reg = <0x0 0x280 0x0 0x4>;
#reset-cells = <1>;
clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
};
};

1
Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
View File

@@ -17,6 +17,7 @@ properties:
- amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
- amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
- amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
- amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs
reg:
maxItems: 1

20
Documentation/devicetree/bindings/reset/ath79-reset.txt
View File

@@ -1,20 +0,0 @@
Binding for Qualcomm Atheros AR7xxx/AR9XXX reset controller
Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required Properties:
- compatible: has to be "qca,<soctype>-reset", "qca,ar7100-reset"
as fallback
- reg: Base address and size of the controllers memory area
- #reset-cells : Specifies the number of cells needed to encode reset
line, should be 1
Example:
reset-controller@1806001c {
compatible = "qca,ar9132-reset", "qca,ar7100-reset";
reg = <0x1806001c 0x4>;
#reset-cells = <1>;
};

23
Documentation/devicetree/bindings/reset/berlin,reset.txt
View File

@@ -1,23 +0,0 @@
Marvell Berlin reset controller
===============================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
The reset controller node must be a sub-node of the chip controller
node on Berlin SoCs.
Required properties:
- compatible: should be "marvell,berlin2-reset"
- #reset-cells: must be set to 2
Example:
chip_rst: reset {
compatible = "marvell,berlin2-reset";
#reset-cells = <2>;
};
&usb_phy0 {
resets = <&chip_rst 0x104 12>;
};

18
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Bitmain BM1880 SoC Reset Controller
===================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: Should be "bitmain,bm1880-reset"
- reg: Offset and length of reset controller space in SCTRL.
- #reset-cells: Must be 1.
Example:
rst: reset-controller@c00 {
compatible = "bitmain,bm1880-reset";
reg = <0xc00 0x8>;
#reset-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Manivannan Sadhasivam <mani@kernel.org>
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/bitmain,bm1880-reset.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Bitmain BM1880 SoC Reset Controller
maintainers:
- Manivannan Sadhasivam <mani@kernel.org>
properties:
compatible:
const: bitmain,bm1880-reset
reg:
maxItems: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
- "#reset-cells"
additionalProperties: false
examples:
- |
rst: reset-controller@c00 {
compatible = "bitmain,bm1880-reset";
reg = <0xc00 0x8>;
#reset-cells = <1>;
};

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Lantiq XWAY SoC RCU reset controller binding
============================================
This binding describes a reset-controller found on the RCU module on Lantiq
XWAY SoCs.
This node has to be a sub node of the Lantiq RCU block.
-------------------------------------------------------------------------------
Required properties:
- compatible : Should be one of
"lantiq,danube-reset"
"lantiq,xrx200-reset"
- reg : Defines the following sets of registers in the parent
syscon device
- Offset of the reset set register
- Offset of the reset status register
- #reset-cells : Specifies the number of cells needed to encode the
reset line, should be 2.
The first cell takes the reset set bit and the
second cell takes the status bit.
-------------------------------------------------------------------------------
Example for the reset-controllers on the xRX200 SoCs:
reset0: reset-controller@10 {
compatible = "lantiq,xrx200-reset";
reg <0x10 0x04>, <0x14 0x04>;
#reset-cells = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/lantiq,reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Lantiq XWAY SoC RCU reset controller
maintainers:
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
description: |
This binding describes a reset-controller found on the RCU module on Lantiq
XWAY SoCs. This node has to be a sub node of the Lantiq RCU block.
properties:
compatible:
enum:
- lantiq,danube-reset
- lantiq,xrx200-reset
reg:
description: |
Defines the following sets of registers in the parent syscon device
Offset of the reset set register
Offset of the reset status register
maxItems: 2
'#reset-cells':
description: |
The first cell takes the reset set bit and the second cell takes the
status bit.
const: 2
required:
- compatible
- reg
- '#reset-cells'
additionalProperties: false
examples:
- |
// On the xRX200 SoCs:
reset0: reset-controller@10 {
compatible = "lantiq,xrx200-reset";
reg = <0x10 0x04>, <0x14 0x04>;
#reset-cells = <2>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2015 Antoine Tenart <atenart@kernel.org>
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/marvell,berlin2-reset.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Marvell Berlin reset controller
maintainers:
- Antoine Tenart <atenart@kernel.org>
description: The reset controller node must be a sub-node of the chip
controller node on Berlin SoCs.
properties:
compatible:
const: marvell,berlin2-reset
"#reset-cells":
const: 2
required:
- compatible
- "#reset-cells"
additionalProperties: false
examples:
- |
chip: chip-control@ea0000 {
reg = <0xea0000 0x400>;
chip_rst: reset {
compatible = "marvell,berlin2-reset";
#reset-cells = <2>;
};
};

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Nuvoton NPCM Reset controller
Required properties:
- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
- reg : specifies physical base address and size of the register.
- #reset-cells: must be set to 2
Optional property:
- nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
NPCM7xx contain four software reset that represent numbers 1 to 4.
If 'nuvoton,sw-reset-number' is not specified software reset is disabled.
Example:
rstc: rstc@f0801000 {
compatible = "nuvoton,npcm750-reset";
reg = <0xf0801000 0x70>;
#reset-cells = <2>;
nuvoton,sw-reset-number = <2>;
};
Specifying reset lines connected to IP NPCM7XX modules
======================================================
example:
spi0: spi@..... {
...
resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
...
};
The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.

50
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nuvoton NPCM Reset controller
maintainers:
- Tomer Maimon <tmaimon77@gmail.com>
properties:
compatible:
const: nuvoton,npcm750-reset
reg:
maxItems: 1
'#reset-cells':
const: 2
nuvoton,sw-reset-number:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 4
description: |
Contains the software reset number to restart the SoC.
If not specified, software reset is disabled.
required:
- compatible
- reg
- '#reset-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
rstc: rstc@f0801000 {
compatible = "nuvoton,npcm750-reset";
reg = <0xf0801000 0x70>;
#reset-cells = <2>;
nuvoton,sw-reset-number = <2>;
};
// Specifying reset lines connected to IP NPCM7XX modules
spi0: spi {
resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2015 Alban Bedel <albeu@free.fr>
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/qca,ar7100-reset.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Atheros AR7xxx/AR9XXX reset controller
maintainers:
- Alban Bedel <albeu@free.fr>
properties:
compatible:
items:
- enum:
- qca,ar9132-reset
- qca,ar9331-reset
- const: qca,ar7100-reset
reg:
maxItems: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
- "#reset-cells"
additionalProperties: false
examples:
- |
reset-controller@1806001c {
compatible = "qca,ar9132-reset", "qca,ar7100-reset";
reg = <0x1806001c 0x4>;
#reset-cells = <1>;
};

1
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@@ -49,6 +49,7 @@ properties:
- renesas,r8a77995-rst # R-Car D3
- renesas,r8a779a0-rst # R-Car V3U
- renesas,r8a779f0-rst # R-Car S4-8
- renesas,r8a779g0-rst # R-Car V4H
reg:
maxItems: 1

33
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Binding for the AXS10x reset controller
This binding describes the ARC AXS10x boards custom IP-block which allows
to control reset signals of selected peripherals. For example DW GMAC, etc...
This block is controlled via memory-mapped register (AKA CREG) which
represents up-to 32 reset lines.
As of today only the following lines are used:
- DW GMAC - line 5
This binding uses the common reset binding[1].
[1] Documentation/devicetree/bindings/reset/reset.txt
Required properties:
- compatible: should be "snps,axs10x-reset".
- reg: should always contain pair address - length: for creg reset
bits register.
- #reset-cells: from common reset binding; Should always be set to 1.
Example:
reset: reset-controller@11220 {
compatible = "snps,axs10x-reset";
#reset-cells = <1>;
reg = <0x11220 0x4>;
};
Specifying reset lines connected to IP modules:
ethernet@.... {
....
resets = <&reset 5>;
....
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/snps,axs10x-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: AXS10x reset controller
maintainers:
- Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
description: |
This binding describes the ARC AXS10x boards custom IP-block which allows
to control reset signals of selected peripherals. For example DW GMAC, etc...
This block is controlled via memory-mapped register (AKA CREG) which
represents up-to 32 reset lines.
As of today only the following lines are used:
- DW GMAC - line 5
properties:
compatible:
const: snps,axs10x-reset
reg:
maxItems: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#reset-cells'
additionalProperties: false
examples:
- |
reset: reset-controller@11220 {
compatible = "snps,axs10x-reset";
#reset-cells = <1>;
reg = <0x11220 0x4>;
};
// Specifying reset lines connected to IP modules:
ethernet {
resets = <&reset 5>;
};

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Altera SOCFPGA Reset Manager
Required properties:
- compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10)
"altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoC
- reg : Should contain 1 register ranges(address and length)
- altr,modrst-offset : Should contain the offset of the first modrst register.
- #reset-cells: 1
Example:
rstmgr@ffd05000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
altr,modrst-offset = <0x10>;
};

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@@ -38,25 +38,49 @@ properties:
minItems: 1
maxItems: 2
clock-names:
oneOf:
- items: # for Pro4, Pro5
- const: gio
- const: link
- items: # for others
- const: link
clock-names: true
resets:
minItems: 1
maxItems: 2
reset-names:
oneOf:
- items: # for Pro4, Pro5
- const: gio
- const: link
- items: # for others
- const: link
reset-names: true
allOf:
- if:
properties:
compatible:
contains:
enum:
- socionext,uniphier-pro4-usb3-reset
- socionext,uniphier-pro5-usb3-reset
- socionext,uniphier-pro4-ahci-reset
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: gio
- const: link
resets:
minItems: 2
maxItems: 2
reset-names:
items:
- const: gio
- const: link
else:
properties:
clocks:
maxItems: 1
clock-names:
const: link
resets:
maxItems: 1
reset-names:
const: link
additionalProperties: false

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STMicroelectronics STi family Sysconfig Picophy SoftReset Controller
=============================================================================
This binding describes a reset controller device that is used to enable and
disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in
the STi family SoC system configuration registers.
The actual action taken when softreset is asserted is hardware dependent.
However, when asserted it may not be possible to access the hardware's
registers and after an assert/deassert sequence the hardware's previous state
may no longer be valid.
Please refer to Documentation/devicetree/bindings/reset/reset.txt
for common reset controller binding usage.
Required properties:
- compatible: Should be "st,stih407-picophyreset"
- #reset-cells: 1, see below
Example:
picophyreset: picophyreset-controller {
compatible = "st,stih407-picophyreset";
#reset-cells = <1>;
};
Specifying picophyreset control of devices
=======================================
Device nodes should specify the reset channel required in their "resets"
property, containing a phandle to the picophyreset device node and an
index specifying which channel to use, as described in
Documentation/devicetree/bindings/reset/reset.txt.
Example:
usb2_picophy0: usbpicophy@0 {
resets = <&picophyreset STIH407_PICOPHY0_RESET>;
};
Macro definitions for the supported reset channels can be found in:
include/dt-bindings/reset/stih407-resets.h

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STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller
=============================================================================
This binding describes a reset controller device that is used to enable and
disable on-chip peripheral controllers such as USB and SATA, using
"powerdown" control bits found in the STi family SoC system configuration
registers. These have been grouped together into a single reset controller
device for convenience.
The actual action taken when powerdown is asserted is hardware dependent.
However, when asserted it may not be possible to access the hardware's
registers and after an assert/deassert sequence the hardware's previous state
may no longer be valid.
Please refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: Should be "st,stih407-powerdown"
- #reset-cells: 1, see below
example:
powerdown: powerdown-controller {
compatible = "st,stih407-powerdown";
#reset-cells = <1>;
};
Specifying powerdown control of devices
=======================================
Device nodes should specify the reset channel required in their "resets"
property, containing a phandle to the powerdown device node and an
index specifying which channel to use, as described in reset.txt
example:
st_dwc3: dwc3@8f94000 {
resets = <&powerdown STIH407_USB3_POWERDOWN>,
};
Macro definitions for the supported reset channels can be found in:
include/dt-bindings/reset/stih407-resets.h

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/st,stih407-picophyreset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STi family Sysconfig Picophy SoftReset Controller
maintainers:
- Peter Griffin <peter.griffin@linaro.org>
description: |
This binding describes a reset controller device that is used to enable and
disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in
the STi family SoC system configuration registers.
The actual action taken when softreset is asserted is hardware dependent.
However, when asserted it may not be possible to access the hardware's
registers and after an assert/deassert sequence the hardware's previous state
may no longer be valid.
properties:
compatible:
const: st,stih407-picophyreset
'#reset-cells':
const: 1
required:
- compatible
- '#reset-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/reset/stih407-resets.h>
picophyreset: picophyreset-controller {
compatible = "st,stih407-picophyreset";
#reset-cells = <1>;
};
// Specifying picophyreset control of devices
usb2_picophy0: usbpicophy {
resets = <&picophyreset STIH407_PICOPHY0_RESET>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/st,stih407-powerdown.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@st.com>
description: |
This binding describes a reset controller device that is used to enable and
disable on-chip peripheral controllers such as USB and SATA, using
"powerdown" control bits found in the STi family SoC system configuration
registers. These have been grouped together into a single reset controller
device for convenience.
The actual action taken when powerdown is asserted is hardware dependent.
However, when asserted it may not be possible to access the hardware's
registers and after an assert/deassert sequence the hardware's previous state
may no longer be valid.
properties:
compatible:
const: st,stih407-powerdown
'#reset-cells':
const: 1
required:
- compatible
- '#reset-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/reset/stih407-resets.h>
powerdown: powerdown-controller {
compatible = "st,stih407-powerdown";
#reset-cells = <1>;
};
// Specifying powerdown control of devices:
st_dwc3: dwc3 {
resets = <&powerdown STIH407_USB3_POWERDOWN>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8MP HDMI blk-ctrl
maintainers:
- Lucas Stach <l.stach@pengutronix.de>
description:
The i.MX8MP HDMMI blk-ctrl is a top-level peripheral providing access to
the NoC and ensuring proper power sequencing of the display pipeline
peripherals located in the HDMI domain of the SoC.
properties:
compatible:
items:
- const: fsl,imx8mp-hdmi-blk-ctrl
- const: syscon
reg:
maxItems: 1
'#power-domain-cells':
const: 1
power-domains:
minItems: 8
maxItems: 8
power-domain-names:
items:
- const: bus
- const: irqsteer
- const: lcdif
- const: pai
- const: pvi
- const: trng
- const: hdmi-tx
- const: hdmi-tx-phy
clocks:
minItems: 4
maxItems: 4
clock-names:
items:
- const: apb
- const: axi
- const: ref_266m
- const: ref_24m
required:
- compatible
- reg
- power-domains
- power-domain-names
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/power/imx8mp-power.h>
blk-ctrl@32fc0000 {
compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
reg = <0x32fc0000 0x23c>;
clocks = <&clk IMX8MP_CLK_HDMI_APB>,
<&clk IMX8MP_CLK_HDMI_ROOT>,
<&clk IMX8MP_CLK_HDMI_REF_266M>,
<&clk IMX8MP_CLK_HDMI_24M>;
clock-names = "apb", "axi", "ref_266m", "ref_24m";
power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>,
<&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>,
<&pgc_hdmimix>, <&pgc_hdmi_phy>;
power-domain-names = "bus", "irqsteer", "lcdif", "pai", "pvi", "trng",
"hdmi-tx", "hdmi-tx-phy";
#power-domain-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8MP Media Block Control
maintainers:
- Paul Elder <paul.elder@ideasonboard.com>
description:
The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
providing access to the NoC and ensuring proper power sequencing of the
peripherals within the MEDIAMIX domain.
properties:
compatible:
items:
- const: fsl,imx8mp-media-blk-ctrl
- const: syscon
reg:
maxItems: 1
'#power-domain-cells':
const: 1
power-domains:
maxItems: 10
power-domain-names:
items:
- const: bus
- const: mipi-dsi1
- const: mipi-csi1
- const: lcdif1
- const: isi
- const: mipi-csi2
- const: lcdif2
- const: isp
- const: dwe
- const: mipi-dsi2
clocks:
items:
- description: The APB clock
- description: The AXI clock
- description: The pixel clock for the first CSI2 receiver (aclk)
- description: The pixel clock for the second CSI2 receiver (aclk)
- description: The pixel clock for the first LCDIF (pix_clk)
- description: The pixel clock for the second LCDIF (pix_clk)
- description: The core clock for the ISP (clk)
- description: The MIPI-PHY reference clock used by DSI
clock-names:
items:
- const: apb
- const: axi
- const: cam1
- const: cam2
- const: disp1
- const: disp2
- const: isp
- const: phy
required:
- compatible
- reg
- '#power-domain-cells'
- power-domains
- power-domain-names
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/power/imx8mp-power.h>
media_blk_ctl: blk-ctl@32ec0000 {
compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
reg = <0x32ec0000 0x138>;
power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
<&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
<&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
<&mipi_phy2_pd>;
power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
"mipi-csi2", "lcdif2", "isp1", "dwe", "mipi-dsi2";
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
"isp", "phy";
#power-domain-cells = <1>;
};
...

10
Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
View File

@@ -31,20 +31,20 @@ Required properties in pwrap device node.
"mediatek,mt8195-pwrap" for MT8195 SoCs
"mediatek,mt8516-pwrap" for MT8516 SoCs
- interrupts: IRQ for pwrap in SOC
- reg-names: Must include the following entries:
- reg-names: "pwrap" is required; "pwrap-bridge" is optional.
"pwrap": Main registers base
"pwrap-bridge": bridge base (IP Pairing)
- reg: Must contain an entry for each entry in reg-names.
- reset-names: Must include the following entries:
"pwrap"
"pwrap-bridge" (IP Pairing)
- resets: Must contain an entry for each entry in reset-names.
- clock-names: Must include the following entries:
"spi": SPI bus clock
"wrap": Main module clock
- clocks: Must contain an entry for each entry in clock-names.
Optional properities:
- reset-names: Some SoCs include the following entries:
"pwrap"
"pwrap-bridge" (IP Pairing)
- resets: Must contain an entry for each entry in reset-names.
- pmic: Using either MediaTek PMIC MFD as the child device of pwrap
See the following for child node definitions:
Documentation/devicetree/bindings/mfd/mt6397.txt

99
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View File

@@ -63,116 +63,23 @@ required:
- ranges
patternProperties:
"^.*@[0-9a-f]+$":
type: object
description: Common properties for GENI Serial Engine based I2C, SPI and
UART controller.
properties:
reg:
description: GENI Serial Engine register address and length.
maxItems: 1
clock-names:
const: se
clocks:
description: Serial engine core clock needed by the device.
maxItems: 1
interconnects:
minItems: 2
maxItems: 3
interconnect-names:
minItems: 2
items:
- const: qup-core
- const: qup-config
- const: qup-memory
required:
- reg
- clock-names
- clocks
"spi@[0-9a-f]+$":
type: object
description: GENI serial engine based SPI controller. SPI in master mode
supports up to 50MHz, up to four chip selects, programmable
data path from 4 bits to 32 bits and numerous protocol
variants.
$ref: /schemas/spi/spi-controller.yaml#
properties:
compatible:
enum:
- qcom,geni-spi
interrupts:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
required:
- compatible
- interrupts
- "#address-cells"
- "#size-cells"
$ref: /schemas/spi/qcom,spi-geni-qcom.yaml#
"i2c@[0-9a-f]+$":
type: object
description: GENI serial engine based I2C controller.
$ref: /schemas/i2c/i2c-controller.yaml#
properties:
compatible:
enum:
- qcom,geni-i2c
interrupts:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
clock-frequency:
description: Desired I2C bus clock frequency in Hz.
default: 100000
required:
- compatible
- interrupts
- "#address-cells"
- "#size-cells"
$ref: /schemas/i2c/qcom,i2c-geni-qcom.yaml#
"serial@[0-9a-f]+$":
type: object
description: GENI Serial Engine based UART Controller.
$ref: /schemas/serial.yaml#
properties:
compatible:
enum:
- qcom,geni-uart
- qcom,geni-debug-uart
interrupts:
minItems: 1
items:
- description: UART core irq
- description: Wakeup irq (RX GPIO)
required:
- compatible
- interrupts
$ref: /schemas/serial/qcom,serial-geni-qcom.yaml#
additionalProperties: false

272
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View File

@@ -0,0 +1,272 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMH RSC
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Resource Power Manager Hardened (RPMH) is the mechanism for communicating
with the hardened resource accelerators on Qualcomm SoCs. Requests to the
resources can be written to the Trigger Command Set (TCS) registers and
using a (addr, val) pair and triggered. Messages in the TCS are then sent in
sequence over an internal bus.
The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
(Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
active/wake resource requests. Multiple such DRVs can exist in a SoC and can
be written to from Linux. The structure of each DRV follows the same template
with a few variations that are captured by the properties here.
A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
have powered off to facilitate idle power saving. TCS could be classified as::
ACTIVE - Triggered by Linux
SLEEP - Triggered by F/W
WAKE - Triggered by F/W
CONTROL - Triggered by F/W
See also:: <dt-bindings/soc/qcom,rpmh-rsc.h>
The order in which they are described in the DT, should match the hardware
configuration.
Requests can be made for the state of a resource, when the subsystem is
active or idle. When all subsystems like Modem, GPU, CPU are idle, the
resource state will be an aggregate of the sleep votes from each of those
subsystems. Clients may request a sleep value for their shared resources in
addition to the active mode requests.
Drivers that want to use the RSC to communicate with RPMH must specify their
bindings as child nodes of the RSC controllers they wish to communicate with.
properties:
compatible:
const: qcom,rpmh-rsc
interrupts:
minItems: 1
maxItems: 4
description:
The interrupt that trips when a message complete/response is received for
this DRV from the accelerators.
Number of interrupts must match number of DRV blocks.
label:
description:
Name for the RSC. The name would be used in trace logs.
qcom,drv-id:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The ID of the DRV in the RSC block that will be used by this controller.
qcom,tcs-config:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
- items:
- description: TCS type
enum: [ 0, 1, 2, 3 ]
- description: Number of TCS
- items:
- description: TCS type
enum: [ 0, 1, 2, 3 ]
- description: Number of TCS
- items:
- description: TCS type
enum: [ 0, 1, 2, 3]
- description: Numbe r of TCS
- items:
- description: TCS type
enum: [ 0, 1, 2, 3 ]
- description: Number of TCS
description: |
The tuple defining the configuration of TCS. Must have two cells which
describe each TCS type. The order of the TCS must match the hardware
configuration.
Cell 1 (TCS Type):: TCS types to be specified::
- ACTIVE_TCS
- SLEEP_TCS
- WAKE_TCS
- CONTROL_TCS
Cell 2 (Number of TCS):: <u32>
qcom,tcs-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The offset of the TCS blocks.
reg:
minItems: 1
maxItems: 4
reg-names:
minItems: 1
items:
- const: drv-0
- const: drv-1
- const: drv-2
- const: drv-3
bcm-voter:
$ref: /schemas/interconnect/qcom,bcm-voter.yaml#
clock-controller:
$ref: /schemas/clock/qcom,rpmhcc.yaml#
power-controller:
$ref: /schemas/power/qcom,rpmpd.yaml#
patternProperties:
'-regulators$':
$ref: /schemas/regulator/qcom,rpmh-regulator.yaml#
required:
- compatible
- interrupts
- qcom,drv-id
- qcom,tcs-config
- qcom,tcs-offset
- reg
- reg-names
additionalProperties: false
examples:
- |
// For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
// 2, the register offsets for DRV2 start at 0D00, the register
// calculations are like this::
// DRV0: 0x179C0000
// DRV2: 0x179C0000 + 0x10000 = 0x179D0000
// DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
// TCS-OFFSET: 0xD00
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
rsc@179c0000 {
compatible = "qcom,rpmh-rsc";
reg = <0x179c0000 0x10000>,
<0x179d0000 0x10000>,
<0x179e0000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
label = "apps_rsc";
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
};
- |
// For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
// register offsets for DRV0 start at 01C00, the register calculations are
// like this::
// DRV0: 0xAF20000
// TCS-OFFSET: 0x1C00
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
rsc@af20000 {
compatible = "qcom,rpmh-rsc";
reg = <0xaf20000 0x10000>;
reg-names = "drv-0";
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
label = "disp_rsc";
qcom,tcs-offset = <0x1c00>;
qcom,drv-id = <0>;
qcom,tcs-config = <ACTIVE_TCS 0>,
<SLEEP_TCS 1>,
<WAKE_TCS 1>,
<CONTROL_TCS 0>;
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
rsc@18200000 {
compatible = "qcom,rpmh-rsc";
reg = <0x18200000 0x10000>,
<0x18210000 0x10000>,
<0x18220000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
label = "apps_rsc";
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 0>;
clock-controller {
compatible = "qcom,sm8350-rpmh-clk";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
};
power-controller {
compatible = "qcom,sm8350-rpmhpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmhpd_opp_table>;
rpmhpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmhpd_opp_ret: opp1 {
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
};
rpmhpd_opp_min_svs: opp2 {
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
rpmhpd_opp_low_svs: opp3 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
rpmhpd_opp_svs: opp4 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
rpmhpd_opp_svs_l1: opp5 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
rpmhpd_opp_nom: opp6 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
rpmhpd_opp_nom_l1: opp7 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
rpmhpd_opp_nom_l2: opp8 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
};
rpmhpd_opp_turbo: opp9 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
rpmhpd_opp_turbo_l1: opp10 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
};
};
bcm-voter {
compatible = "qcom,bcm-voter";
};
};

7
Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
View File

@@ -12,7 +12,7 @@ description: |
to vote for state of the system resources, such as clocks, regulators and bus
frequencies.
The SMD information for the RPM edge should be filled out. See qcom,smd.txt
The SMD information for the RPM edge should be filled out. See qcom,smd.yaml
for the required edge properties. All SMD related properties will reside
within the RPM node itself.
@@ -25,7 +25,8 @@ description: |
rpm_requests.
maintainers:
- Kathiravan T <kathirav@codeaurora.org>
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
properties:
compatible:
@@ -83,7 +84,7 @@ examples:
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm_requests {
rpm-requests {
compatible = "qcom,rpm-msm8974";
qcom,smd-channels = "rpm_requests";

98
Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt
View File

@@ -1,98 +0,0 @@
Qualcomm Shared Memory Driver (SMD) binding
This binding describes the Qualcomm Shared Memory Driver, a fifo based
communication channel for sending data between the various subsystems in
Qualcomm platforms.
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be "qcom,smd"
= EDGES
Each subnode of the SMD node represents a remote subsystem or a remote
processor of some sort - or in SMD language an "edge". The name of the edges
are not important.
The edge is described by the following properties:
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the IRQ used by the remote processor to
signal this processor about communication related updates
- mboxes:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the associated doorbell in APCS, as described
in mailbox/mailbox.txt
- qcom,ipc:
Usage: required, unless mboxes is specified
Value type: <prop-encoded-array>
Definition: three entries specifying the outgoing ipc bit used for
signaling the remote processor:
- phandle to a syscon node representing the apcs registers
- u32 representing offset to the register within the syscon
- u32 representing the ipc bit within the register
- qcom,smd-edge:
Usage: required
Value type: <u32>
Definition: the identifier of the remote processor in the smd channel
allocation table
- qcom,remote-pid:
Usage: optional
Value type: <u32>
Definition: the identifier for the remote processor as known by the rest
of the system.
- label:
Usage: optional
Value type: <string>
Definition: name of the edge, used for debugging and identification
purposes. The node name will be used if this is not
present.
= SMD DEVICES
In turn, subnodes of the "edges" represent devices tied to SMD channels on that
"edge". The names of the devices are not important. The properties of these
nodes are defined by the individual bindings for the SMD devices - but must
contain the following property:
- qcom,smd-channels:
Usage: required
Value type: <stringlist>
Definition: a list of channels tied to this device, used for matching
the device to channels
= EXAMPLE
The following example represents a smd node, with one edge representing the
"rpm" subsystem. For the "rpm" subsystem we have a device tied to the
"rpm_request" channel.
apcs: syscon@f9011000 {
compatible = "syscon";
reg = <0xf9011000 0x1000>;
};
smd {
compatible = "qcom,smd";
rpm {
interrupts = <0 168 1>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm_requests {
compatible = "qcom,rpm-msm8974";
qcom,smd-channels = "rpm_requests";
...
};
};
};

137
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@@ -0,0 +1,137 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,smd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Shared Memory Driver
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
The Qualcomm Shared Memory Driver is a FIFO based communication channel for
sending data between the various subsystems in Qualcomm platforms.
properties:
compatible:
const: qcom,smd
patternProperties:
"^.*-edge|rpm$":
type: object
description:
Each subnode of the SMD node represents a remote subsystem or a remote
processor of some sort - or in SMD language an "edge". The name of the
edges are not important.
properties:
interrupts:
maxItems: 1
label:
$ref: /schemas/types.yaml#/definitions/string
description:
Name of the edge, used for debugging and identification purposes. The
node name will be used if this is not present.
mboxes:
maxItems: 1
description:
Reference to the mailbox representing the outgoing doorbell in APCS for
this client.
qcom,ipc:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to a syscon node representing the APCS registers
- description: u32 representing offset to the register within the syscon
- description: u32 representing the ipc bit within the register
description:
Three entries specifying the outgoing ipc bit used for signaling the
remote processor.
qcom,smd-edge:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The identifier of the remote processor in the smd channel allocation
table.
qcom,remote-pid:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The identifier for the remote processor as known by the rest of the
system.
# Binding for edge subnodes is not complete
patternProperties:
"^rpm-requests$":
type: object
description:
In turn, subnodes of the "edges" represent devices tied to SMD
channels on that "edge". The names of the devices are not
important. The properties of these nodes are defined by the
individual bindings for the SMD devices.
properties:
qcom,smd-channels:
$ref: /schemas/types.yaml#/definitions/string-array
minItems: 1
maxItems: 32
description:
A list of channels tied to this device, used for matching the
device to channels.
required:
- compatible
- qcom,smd-channels
additionalProperties: true
required:
- interrupts
- qcom,smd-edge
oneOf:
- required:
- mboxes
- required:
- qcom,ipc
additionalProperties: false
required:
- compatible
additionalProperties: false
examples:
# The following example represents a smd node, with one edge representing the
# "rpm" subsystem. For the "rpm" subsystem we have a device tied to the
# "rpm_request" channel.
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
shared-memory {
compatible = "qcom,smd";
rpm {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm-requests {
compatible = "qcom,rpm-msm8974";
qcom,smd-channels = "rpm_requests";
clock-controller {
compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
#clock-cells = <1>;
};
};
};
};

104
Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt
View File

@@ -1,104 +0,0 @@
Qualcomm Shared Memory State Machine
The Shared Memory State Machine facilitates broadcasting of single bit state
information between the processors in a Qualcomm SoC. Each processor is
assigned 32 bits of state that can be modified. A processor can through a
matrix of bitmaps signal subscription of notifications upon changes to a
certain bit owned by a certain remote processor.
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,smsm"
- qcom,ipc-N:
Usage: required
Value type: <prop-encoded-array>
Definition: three entries specifying the outgoing ipc bit used for
signaling the N:th remote processor
- phandle to a syscon node representing the apcs registers
- u32 representing offset to the register within the syscon
- u32 representing the ipc bit within the register
- qcom,local-host:
Usage: optional
Value type: <u32>
Definition: identifier of the local processor in the list of hosts, or
in other words specifier of the column in the subscription
matrix representing the local processor
defaults to host 0
- #address-cells:
Usage: required
Value type: <u32>
Definition: must be 1
- #size-cells:
Usage: required
Value type: <u32>
Definition: must be 0
= SUBNODES
Each processor's state bits are described by a subnode of the smsm device node.
Nodes can either be flagged as an interrupt-controller to denote a remote
processor's state bits or the local processors bits. The node names are not
important.
- reg:
Usage: required
Value type: <u32>
Definition: specifies the offset, in words, of the first bit for this
entry
- #qcom,smem-state-cells:
Usage: required for local entry
Value type: <u32>
Definition: must be 1 - denotes bit number
- interrupt-controller:
Usage: required for remote entries
Value type: <empty>
Definition: marks the entry as a interrupt-controller and the state bits
to belong to a remote processor
- #interrupt-cells:
Usage: required for remote entries
Value type: <u32>
Definition: must be 2 - denotes bit number and IRQ flags
- interrupts:
Usage: required for remote entries
Value type: <prop-encoded-array>
Definition: one entry specifying remote IRQ used by the remote processor
to signal changes of its state bits
= EXAMPLE
The following example shows the SMEM setup for controlling properties of the
wireless processor, defined from the 8974 apps processor's point-of-view. It
encompasses one outbound entry and the outgoing interrupt for the wireless
processor.
smsm {
compatible = "qcom,smsm";
#address-cells = <1>;
#size-cells = <0>;
qcom,ipc-3 = <&apcs 8 19>;
apps_smsm: apps@0 {
reg = <0>;
#qcom,smem-state-cells = <1>;
};
wcnss_smsm: wcnss@7 {
reg = <7>;
interrupts = <0 144 1>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

138
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@@ -0,0 +1,138 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,smsm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Shared Memory State Machine
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
The Shared Memory State Machine facilitates broadcasting of single bit state
information between the processors in a Qualcomm SoC. Each processor is
assigned 32 bits of state that can be modified. A processor can through a
matrix of bitmaps signal subscription of notifications upon changes to a
certain bit owned by a certain remote processor.
properties:
compatible:
const: qcom,smsm
'#address-cells':
const: 1
qcom,local-host:
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
description:
Identifier of the local processor in the list of hosts, or in other words
specifier of the column in the subscription matrix representing the local
processor.
'#size-cells':
const: 0
patternProperties:
"^qcom,ipc-[1-4]$":
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to a syscon node representing the APCS registers
- description: u32 representing offset to the register within the syscon
- description: u32 representing the ipc bit within the register
description:
Three entries specifying the outgoing ipc bit used for signaling the N:th
remote processor.
"@[0-9a-f]$":
type: object
description:
Each processor's state bits are described by a subnode of the SMSM device
node. Nodes can either be flagged as an interrupt-controller to denote a
remote processor's state bits or the local processors bits. The node
names are not important.
properties:
reg:
maxItems: 1
interrupt-controller:
description:
Marks the entry as a interrupt-controller and the state bits to
belong to a remote processor.
'#interrupt-cells':
const: 2
interrupts:
maxItems: 1
description:
One entry specifying remote IRQ used by the remote processor to
signal changes of its state bits.
'#qcom,smem-state-cells':
$ref: /schemas/types.yaml#/definitions/uint32
const: 1
description:
Required for local entry. Denotes bit number.
required:
- reg
oneOf:
- required:
- '#qcom,smem-state-cells'
- required:
- interrupt-controller
- '#interrupt-cells'
- interrupts
additionalProperties: false
required:
- compatible
- '#address-cells'
- '#size-cells'
anyOf:
- required:
- qcom,ipc-1
- required:
- qcom,ipc-2
- required:
- qcom,ipc-3
- required:
- qcom,ipc-4
additionalProperties: false
examples:
# The following example shows the SMEM setup for controlling properties of
# the wireless processor, defined from the 8974 apps processor's
# point-of-view. It encompasses one outbound entry and the outgoing interrupt
# for the wireless processor.
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
shared-memory {
compatible = "qcom,smsm";
#address-cells = <1>;
#size-cells = <0>;
qcom,ipc-3 = <&apcs 8 19>;
apps_smsm: apps@0 {
reg = <0>;
#qcom,smem-state-cells = <1>;
};
wcnss_smsm: wcnss@7 {
reg = <7>;
interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

131
Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt
View File

@@ -1,131 +0,0 @@
Qualcomm WCNSS Binding
This binding describes the Qualcomm WCNSS hardware. It consists of control
block and a BT, WiFi and FM radio block, all using SMD as command channels.
- compatible:
Usage: required
Value type: <string>
Definition: must be: "qcom,wcnss",
- qcom,smd-channel:
Usage: required
Value type: <string>
Definition: standard SMD property specifying the SMD channel used for
communication with the WiFi firmware.
Should be "WCNSS_CTRL".
- qcom,mmio:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to a node specifying the wcnss "ccu" and "dxe"
register blocks. The node must be compatible with one of
the following:
"qcom,riva",
"qcom,pronto"
- firmware-name:
Usage: optional
Value type: <string>
Definition: specifies the relative firmware image path for the WLAN NV
blob. Defaults to "wlan/prima/WCNSS_qcom_wlan_nv.bin" if
not specified.
= SUBNODES
The subnodes of the wcnss node are optional and describe the individual blocks in
the WCNSS.
== Bluetooth
The following properties are defined to the bluetooth node:
- compatible:
Usage: required
Value type: <string>
Definition: must be:
"qcom,wcnss-bt"
- local-bd-address:
Usage: optional
Value type: <u8 array>
Definition: see Documentation/devicetree/bindings/net/bluetooth.txt
== WiFi
The following properties are defined to the WiFi node:
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,wcnss-wlan",
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the "rx" and "tx" interrupts
- interrupt-names:
Usage: required
Value type: <stringlist>
Definition: must contain "rx" and "tx"
- qcom,smem-state:
Usage: required
Value type: <prop-encoded-array>
Definition: should reference the tx-enable and tx-rings-empty SMEM states
- qcom,smem-state-names:
Usage: required
Value type: <stringlist>
Definition: must contain "tx-enable" and "tx-rings-empty"
= EXAMPLE
The following example represents a SMD node, with one edge representing the
"pronto" subsystem, with the wcnss device and its wcn3680 BT and WiFi blocks
described; as found on the 8974 platform.
smd {
compatible = "qcom,smd";
pronto-edge {
interrupts = <0 142 1>;
qcom,ipc = <&apcs 8 17>;
qcom,smd-edge = <6>;
wcnss {
compatible = "qcom,wcnss";
qcom,smd-channels = "WCNSS_CTRL";
#address-cells = <1>;
#size-cells = <1>;
qcom,mmio = <&pronto>;
bt {
compatible = "qcom,wcnss-bt";
/* BD address 00:11:22:33:44:55 */
local-bd-address = [ 55 44 33 22 11 00 ];
};
wlan {
compatible = "qcom,wcnss-wlan";
interrupts = <0 145 0>, <0 146 0>;
interrupt-names = "tx", "rx";
qcom,smem-state = <&apps_smsm 10>, <&apps_smsm 9>;
qcom,smem-state-names = "tx-enable", "tx-rings-empty";
};
};
};
};
soc {
pronto: pronto {
compatible = "qcom,pronto";
reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
reg-names = "ccu", "dxe", "pmu";
};
};

137
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View File

@@ -0,0 +1,137 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,wcnss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm WCNSS
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
description:
The Qualcomm WCNSS hardware consists of control block and a BT, WiFi and FM
radio block, all using SMD as command channels.
properties:
compatible:
const: qcom,wcnss
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
default: "wlan/prima/WCNSS_qcom_wlan_nv.bin"
description:
Relative firmware image path for the WLAN NV blob.
qcom,mmio:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Reference to a node specifying the wcnss "ccu" and "dxe" register blocks.
The node must be compatible with one of the following::
- qcom,riva"
- qcom,pronto"
qcom,smd-channels:
$ref: /schemas/types.yaml#/definitions/string
const: WCNSS_CTRL
description:
Standard SMD property specifying the SMD channel used for communication
with the WiFi firmware.
bluetooth:
type: object
additionalProperties: false
properties:
compatible:
const: qcom,wcnss-bt
local-bd-address:
$ref: /schemas/types.yaml#/definitions/uint8-array
maxItems: 6
description:
See Documentation/devicetree/bindings/net/bluetooth.txt
required:
- compatible
wifi:
additionalProperties: false
type: object
properties:
compatible:
const: qcom,wcnss-wlan
interrupts:
maxItems: 2
interrupt-names:
items:
- const: tx
- const: rx
qcom,smem-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 2
description:
Should reference the tx-enable and tx-rings-empty SMEM states.
qcom,smem-state-names:
$ref: /schemas/types.yaml#/definitions/string-array
items:
- const: tx-enable
- const: tx-rings-empty
description:
Names of SMEM states.
required:
- compatible
- interrupts
- interrupt-names
- qcom,smem-states
- qcom,smem-state-names
required:
- compatible
- qcom,mmio
- qcom,smd-channels
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
smd-edge {
interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 17>;
qcom,smd-edge = <6>;
qcom,remote-pid = <4>;
label = "pronto";
wcnss {
compatible = "qcom,wcnss";
qcom,smd-channels = "WCNSS_CTRL";
qcom,mmio = <&pronto>;
bluetooth {
compatible = "qcom,wcnss-bt";
/* BD address 00:11:22:33:44:55 */
local-bd-address = [ 55 44 33 22 11 00 ];
};
wifi {
compatible = "qcom,wcnss-wlan";
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
qcom,smem-state-names = "tx-enable", "tx-rings-empty";
};
};
};

137
Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
View File

@@ -1,137 +0,0 @@
RPMH RSC:
------------
Resource Power Manager Hardened (RPMH) is the mechanism for communicating with
the hardened resource accelerators on Qualcomm SoCs. Requests to the resources
can be written to the Trigger Command Set (TCS) registers and using a (addr,
val) pair and triggered. Messages in the TCS are then sent in sequence over an
internal bus.
The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
(Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
active/wake resource requests. Multiple such DRVs can exist in a SoC and can
be written to from Linux. The structure of each DRV follows the same template
with a few variations that are captured by the properties here.
A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
have powered off to facilitate idle power saving. TCS could be classified as -
ACTIVE /* Triggered by Linux */
SLEEP /* Triggered by F/W */
WAKE /* Triggered by F/W */
CONTROL /* Triggered by F/W */
The order in which they are described in the DT, should match the hardware
configuration.
Requests can be made for the state of a resource, when the subsystem is active
or idle. When all subsystems like Modem, GPU, CPU are idle, the resource state
will be an aggregate of the sleep votes from each of those subsystems. Clients
may request a sleep value for their shared resources in addition to the active
mode requests.
Properties:
- compatible:
Usage: required
Value type: <string>
Definition: Should be "qcom,rpmh-rsc".
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: The first register specifies the base address of the
DRV(s). The number of DRVs in the dependent on the RSC.
The tcs-offset specifies the start address of the
TCS in the DRVs.
- reg-names:
Usage: required
Value type: <string>
Definition: Maps the register specified in the reg property. Must be
"drv-0", "drv-1", "drv-2" etc and "tcs-offset". The
- interrupts:
Usage: required
Value type: <prop-encoded-interrupt>
Definition: The interrupt that trips when a message complete/response
is received for this DRV from the accelerators.
- qcom,drv-id:
Usage: required
Value type: <u32>
Definition: The id of the DRV in the RSC block that will be used by
this controller.
- qcom,tcs-config:
Usage: required
Value type: <prop-encoded-array>
Definition: The tuple defining the configuration of TCS.
Must have 2 cells which describe each TCS type.
<type number_of_tcs>.
The order of the TCS must match the hardware
configuration.
- Cell #1 (TCS Type): TCS types to be specified -
ACTIVE_TCS
SLEEP_TCS
WAKE_TCS
CONTROL_TCS
- Cell #2 (Number of TCS): <u32>
- label:
Usage: optional
Value type: <string>
Definition: Name for the RSC. The name would be used in trace logs.
Drivers that want to use the RSC to communicate with RPMH must specify their
bindings as child nodes of the RSC controllers they wish to communicate with.
Example 1:
For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the
register offsets for DRV2 start at 0D00, the register calculations are like
this -
DRV0: 0x179C0000
DRV2: 0x179C0000 + 0x10000 = 0x179D0000
DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
TCS-OFFSET: 0xD00
apps_rsc: rsc@179c0000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x179c0000 0x10000>,
<0x179d0000 0x10000>,
<0x179e0000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
};
Example 2:
For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
register offsets for DRV0 start at 01C00, the register calculations are like
this -
DRV0: 0xAF20000
TCS-OFFSET: 0x1C00
disp_rsc: rsc@af20000 {
label = "disp_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0xaf20000 0x10000>;
reg-names = "drv-0";
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0x1c00>;
qcom,drv-id = <0>;
qcom,tcs-config = <ACTIVE_TCS 0>,
<SLEEP_TCS 1>,
<WAKE_TCS 1>,
<CONTROL_TCS 0>;
};

7
Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml → Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml
View File

@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#"
$id: "http://devicetree.org/schemas/soc/renesas/renesas,rzg2l-sysc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Renesas RZ/{G2L,V2L} System Controller (SYSC)
@@ -10,8 +10,8 @@ maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description:
The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI
and supports following functions,
The RZ/{G2L,V2L}-alike System Controller (SYSC) performs system control of
the LSI and supports following functions,
- External terminal state capture function
- 34-bit address space access function
- Low power consumption control
@@ -20,6 +20,7 @@ description:
properties:
compatible:
enum:
- renesas,r9a07g043-sysc # RZ/G2UL
- renesas,r9a07g044-sysc # RZ/G2{L,LC}
- renesas,r9a07g054-sysc # RZ/V2L

3
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
View File

@@ -15,6 +15,9 @@ properties:
- items:
- enum:
- rockchip,rk3288-sgrf
- rockchip,rk3566-pipe-grf
- rockchip,rk3568-pipe-grf
- rockchip,rk3568-pipe-phy-grf
- rockchip,rk3568-usb2phy-grf
- rockchip,rv1108-usbgrf
- const: syscon

2
Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
View File

@@ -77,7 +77,7 @@ patternProperties:
description: Child node describing underlying UART/serial
"^spi@[0-9a-f]+$":
type: object
$ref: /schemas/spi/samsung,spi.yaml
description: Child node describing underlying SPI
required:

1
Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
View File

@@ -26,6 +26,7 @@ properties:
- allwinner,sun8i-r40-spi
- allwinner,sun50i-h6-spi
- allwinner,sun50i-h616-spi
- allwinner,suniv-f1c100s-spi
- const: allwinner,sun8i-h3-spi
reg:

39
Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt
View File

@@ -1,39 +0,0 @@
GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
The QUP v3 core is a GENI based AHB slave that provides a common data path
(an output FIFO and an input FIFO) for serial peripheral interface (SPI)
mini-core.
SPI in master mode supports up to 50MHz, up to four chip selects, programmable
data path from 4 bits to 32 bits and numerous protocol variants.
Required properties:
- compatible: Must contain "qcom,geni-spi".
- reg: Must contain SPI register location and length.
- interrupts: Must contain SPI controller interrupts.
- clock-names: Must contain "se".
- clocks: Serial engine core clock needed by the device.
- #address-cells: Must be <1> to define a chip select address on
the SPI bus.
- #size-cells: Must be <0>.
SPI Controller nodes must be child of GENI based Qualcomm Universal
Peripharal. Please refer GENI based QUP wrapper controller node bindings
described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml.
SPI slave nodes must be children of the SPI master node and conform to SPI bus
binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.
Example:
spi0: spi@a84000 {
compatible = "qcom,geni-spi";
reg = <0xa84000 0x4000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qup_1_spi_2_active>;
pinctrl-1 = <&qup_1_spi_2_sleep>;
#address-cells = <1>;
#size-cells = <0>;
};

116
Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml Normal file
View File

@@ -0,0 +1,116 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
The QUP v3 core is a GENI based AHB slave that provides a common data path
(an output FIFO and an input FIFO) for serial peripheral interface (SPI)
mini-core.
SPI in master mode supports up to 50MHz, up to four chip selects,
programmable data path from 4 bits to 32 bits and numerous protocol variants.
SPI Controller nodes must be child of GENI based Qualcomm Universal
Peripharal. Please refer GENI based QUP wrapper controller node bindings
described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml.
allOf:
- $ref: /schemas/spi/spi-controller.yaml#
properties:
compatible:
const: qcom,geni-spi
clocks:
maxItems: 1
clock-names:
const: se
dmas:
maxItems: 2
dma-names:
items:
- const: tx
- const: rx
interconnects:
maxItems: 2
interconnect-names:
items:
- const: qup-core
- const: qup-config
interrupts:
maxItems: 1
operating-points-v2: true
power-domains:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- interrupts
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
#include <dt-bindings/interconnect/qcom,sc7180.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
spi@880000 {
compatible = "qcom,geni-spi";
reg = <0x00880000 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
};
- |
#include <dt-bindings/dma/qcom-gpi.h>
spi@884000 {
compatible = "qcom,geni-spi";
reg = <0x00884000 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
};

25
Documentation/devicetree/bindings/timer/renesas,16bit-timer.txt
View File

@@ -1,25 +0,0 @@
* Renesas H8/300 16bit timer
The 16bit timer is a 16bit timer/counter with configurable clock inputs and
programmable compare match.
Required Properties:
- compatible: must contain "renesas,16bit-timer"
- reg: base address and length of the registers block for the timer module.
- interrupts: interrupt-specifier for the timer, IMIA
- clocks: a list of phandle, one for each entry in clock-names.
- clock-names: must contain "peripheral_clk" for the functional clock.
- renesas,channel: timer channel number.
Example:
timer16: timer@ffff68 {
compatible = "reneas,16bit-timer";
reg = <0xffff68 8>, <0xffff60 8>;
interrupts = <24>;
renesas,channel = <0>;
clocks = <&pclk>;
clock-names = "peripheral_clk";
};

25
Documentation/devicetree/bindings/timer/renesas,8bit-timer.txt
View File

@@ -1,25 +0,0 @@
* Renesas H8/300 8bit timer
The 8bit timer is a 8bit timer/counter with configurable clock inputs and
programmable compare match.
This implement only supported cascade mode.
Required Properties:
- compatible: must contain "renesas,8bit-timer"
- reg: base address and length of the registers block for the timer module.
- interrupts: interrupt-specifier for the timer, CMIA and TOVI
- clocks: a list of phandle, one for each entry in clock-names.
- clock-names: must contain "fck" for the functional clock.
Example:
timer8_0: timer@ffff80 {
compatible = "renesas,8bit-timer";
reg = <0xffff80 10>;
interrupts = <36>;
clocks = <&fclk>;
clock-names = "fck";
};

67
Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
View File

@@ -19,9 +19,20 @@ description: |+
properties:
compatible:
enum:
- samsung,exynos4210-mct
- samsung,exynos4412-mct
oneOf:
- enum:
- samsung,exynos4210-mct
- samsung,exynos4412-mct
- items:
- enum:
- samsung,exynos3250-mct
- samsung,exynos5250-mct
- samsung,exynos5260-mct
- samsung,exynos5420-mct
- samsung,exynos5433-mct
- samsung,exynos850-mct
- tesla,fsd-mct
- const: samsung,exynos4210-mct
clocks:
maxItems: 2
@@ -62,6 +73,56 @@ required:
- interrupts
- reg
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos3250-mct
then:
properties:
interrupts:
minItems: 8
maxItems: 8
- if:
properties:
compatible:
contains:
const: samsung,exynos5250-mct
then:
properties:
interrupts:
minItems: 6
maxItems: 6
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos5260-mct
- samsung,exynos5420-mct
- samsung,exynos5433-mct
- samsung,exynos850-mct
then:
properties:
interrupts:
minItems: 12
maxItems: 12
- if:
properties:
compatible:
contains:
enum:
- tesla,fsd-mct
then:
properties:
interrupts:
minItems: 16
maxItems: 16
additionalProperties: false
examples:

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@@ -1201,6 +1201,8 @@ patternProperties:
description: StorLink Semiconductors, Inc.
"^storm,.*":
description: Storm Semiconductor, Inc.
"^storopack,.*":
description: Storopack
"^summit,.*":
description: Summit microelectronics
"^sunchip,.*":

24
Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
View File

@@ -26,10 +26,8 @@ properties:
- allwinner,sun50i-h616-wdt
- allwinner,sun50i-r329-wdt
- allwinner,sun50i-r329-wdt-reset
- allwinner,suniv-f1c100s-wdt
- const: allwinner,sun6i-a31-wdt
- items:
- const: allwinner,suniv-f1c100s-wdt
- const: allwinner,sun4i-a10-wdt
- const: allwinner,sun20i-d1-wdt
- items:
- const: allwinner,sun20i-d1-wdt-reset
@@ -41,14 +39,8 @@ properties:
clocks:
minItems: 1
items:
- description: High-frequency oscillator input, divided internally
- description: Low-frequency oscillator input, only found on some variants
clock-names:
minItems: 1
items:
- const: hosc
- const: losc
- description: 32 KHz input clock
- description: secondary clock source
interrupts:
maxItems: 1
@@ -73,9 +65,14 @@ then:
properties:
clocks:
minItems: 2
items:
- description: High-frequency oscillator input, divided internally
- description: Low-frequency oscillator input
clock-names:
minItems: 2
items:
- const: hosc
- const: losc
required:
- clock-names
@@ -85,9 +82,6 @@ else:
clocks:
maxItems: 1
clock-names:
maxItems: 1
unevaluatedProperties: false
examples:

1
Documentation/features/core/cBPF-JIT/arch-support.txt
View File

@@ -11,7 +11,6 @@
| arm: | TODO |
| arm64: | TODO |
| csky: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| m68k: | TODO |

1
Documentation/features/core/eBPF-JIT/arch-support.txt
View File

@@ -11,7 +11,6 @@
| arm: | ok |
| arm64: | ok |
| csky: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| m68k: | TODO |

1
Documentation/features/core/generic-idle-thread/arch-support.txt
View File

@@ -11,7 +11,6 @@
| arm: | ok |
| arm64: | ok |
| csky: | ok |
| h8300: | TODO |
| hexagon: | ok |
| ia64: | ok |
| m68k: | TODO |

1
Documentation/features/core/jump-labels/arch-support.txt
View File

@@ -11,7 +11,6 @@
| arm: | ok |
| arm64: | ok |
| csky: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| m68k: | TODO |

1
Documentation/features/core/thread-info-in-task/arch-support.txt
View File

@@ -11,7 +11,6 @@
| arm: | ok |
| arm64: | ok |
| csky: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| m68k: | TODO |

1
Documentation/features/core/tracehook/arch-support.txt
View File

@@ -11,7 +11,6 @@
| arm: | ok |
| arm64: | ok |
| csky: | ok |
| h8300: | TODO |
| hexagon: | ok |
| ia64: | ok |
| m68k: | TODO |

1
Documentation/features/debug/KASAN/arch-support.txt
View File

@@ -11,7 +11,6 @@
| arm: | ok |
| arm64: | ok |
| csky: | TODO |
| h8300: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| m68k: | TODO |

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