shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-05 10:31:46 +09:00
Code Issues Packages Projects Releases Wiki Activity

Merge commit 'fc59a282e70cd4ab12cc1ec7ebc1e9e442a351f7'

Browse Source 
* commit 'fc59a282e70cd4ab12cc1ec7ebc1e9e442a351f7':
  PCI: rockchip: dw: Add rockchip,wait-for-link-ms support
  memory: dsmc: fix bug in multi cs and region
  net: rfkill: rfkill-wlan: fix compilation error
  phy: rockchip: usbdp: Fix LFPS detect threshold control

Change-Id: I64b9ba7695d0d267e4065f5b2325796bf5649f2b
This commit is contained in:
Tao Huang
2024-10-22 18:59:39 +08:00
parent 8a9ca1a1ff fc59a282e7
commit bcc12a2c4a
6 changed files with 23 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/memory/rockchip/dsmc-controller.c
View File

@@ -295,8 +295,12 @@ static int dsmc_ctrller_cfg_for_lb(struct rockchip_dsmc *dsmc, uint32_t cs)
dsmc->regs + DSMC_RGN0_ATTR(cs) + 4 * i);
}
/* clear and enable interrupt */
writel(INT_STATUS(cfg->int_en), dsmc->regs + DSMC_INT_STATUS);
writel(INT_EN(cfg->int_en), dsmc->regs + DSMC_INT_EN);
REG_CLRSETBITS(dsmc, DSMC_INT_STATUS,
INT_STATUS_MASK(cfg->int_en),
INT_STATUS(cfg->int_en));
REG_CLRSETBITS(dsmc, DSMC_INT_EN,
INT_EN_MASK(cfg->int_en),
INT_EN(cfg->int_en));
if (dsmc->cfg.dma_req_mux_offset && (cs < 2))
REG_CLRSETBITS(dsmc, dsmc->cfg.dma_req_mux_offset,

1
drivers/memory/rockchip/dsmc-host.c
View File

@@ -278,6 +278,7 @@ static int dsmc_reg_remap(struct device *dev, struct dsmc_ctrl_config *cfg,
region_map->size,
DSMC_MEM_ATTRIBUTE_NO_CACHE);
} else if (cfg->cs_cfg[cs].device_type == DSMC_LB_DEVICE) {
num = 0;
for (rgn = 0; rgn < DSMC_LB_MAX_RGN; rgn++) {
if (!cfg->cs_cfg[cs].slv_rgn[rgn].status)
continue;

4
drivers/memory/rockchip/dsmc-host.h
View File

@@ -58,12 +58,12 @@
/* INT_EN */
#define INT_EN_SHIFT 0
#define INT_EN_MASK 0xf
#define INT_EN_MASK(cs) (0x1 << (cs))
#define INT_EN(cs) (0x1 << (cs))
/* INT_STATUS */
#define INT_STATUS_SHIFT 0
#define INT_STATUS_MASK 0xf
#define INT_STATUS_MASK(cs) (0x1 << (cs))
#define INT_STATUS(cs) (0x1 << (cs))
/* INT_MASK */

15
drivers/pci/controller/dwc/pcie-dw-rockchip.c
View File

@@ -127,6 +127,7 @@ struct rk_pcie {
struct gpio_desc *rst_gpio;
u32 perst_inactive_ms;
u32 s2r_perst_inactive_ms;
u32 wait_for_link_ms;
struct gpio_desc *prsnt_gpio;
struct dma_trx_obj *dma_obj;
bool in_suspend;
@@ -398,12 +399,14 @@ static int rk_pcie_establish_link(struct dw_pcie *pci)
gpiod_set_value_cansleep(rk_pcie->rst_gpio, 1);
/*
* Add this 1ms delay because we observe link is always up stably after it and
* could help us save 20ms for scanning devices.
* Add this delay because we observe devices need a period of time to be able to
* work, so the link is always up stably after it. And the default 1ms could help us
* save 20ms for scanning devices. If the devices need longer than 2s to be able to
* work, please change wait_for_link_ms via dts.
*/
usleep_range(1000, 1100);
for (retries = 0; retries < 100; retries++) {
for (retries = 0; retries < rk_pcie->wait_for_link_ms / 20; retries++) {
if (dw_pcie_link_up(pci)) {
/*
* We may be here in case of L0 in Gen1. But if EP is capable
@@ -427,7 +430,7 @@ static int rk_pcie_establish_link(struct dw_pcie *pci)
dev_info_ratelimited(pci->dev, "PCIe Linking... LTSSM is 0x%x\n",
rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
rk_pcie_debug_dump(rk_pcie);
msleep(20);
usleep_range(20000, 21000);
}
/*
@@ -682,6 +685,10 @@ static int rk_pcie_resource_get(struct platform_device *pdev,
&rk_pcie->s2r_perst_inactive_ms))
rk_pcie->s2r_perst_inactive_ms = rk_pcie->perst_inactive_ms;
device_property_read_u32(&pdev->dev, "rockchip,wait-for-link-ms",
&rk_pcie->wait_for_link_ms);
rk_pcie->wait_for_link_ms = max_t(u32, rk_pcie->wait_for_link_ms, 2000);
rk_pcie->prsnt_gpio = devm_gpiod_get_optional(&pdev->dev, "prsnt", GPIOD_IN);
if (IS_ERR_OR_NULL(rk_pcie->prsnt_gpio))
dev_info(&pdev->dev, "invalid prsnt-gpios property in node\n");

3
drivers/phy/rockchip/phy-rockchip-usbdp.c
View File

@@ -401,7 +401,8 @@ static const struct reg_sequence udphy_init_sequence[] = {
{0x0070, 0x7D}, {0x0074, 0x68},
{0x0AF4, 0x1A}, {0x1AF4, 0x1A},
{0x0440, 0x3F}, {0x10D4, 0x08},
{0x20D4, 0x08}, {0x0024, 0x6e}
{0x20D4, 0x08}, {0x0024, 0x6e},
{0x09C0, 0x0A}, {0x19C0, 0x0A}
};
static inline int grfreg_write(struct regmap *base,

2
net/rfkill/rfkill-wlan.c
View File

@@ -434,7 +434,7 @@ static int get_wifi_addr_vendor(unsigned char *addr)
LOG("%s: rk_vendor_read wifi mac address failed (%d)\n",
__func__, ret);
#ifdef CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR
random_ether_addr(addr);
eth_random_addr(addr);
LOG("%s: generate random wifi mac address: "
"%02x:%02x:%02x:%02x:%02x:%02x\n",
__func__, addr[0], addr[1], addr[2], addr[3], addr[4],