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phy: rockchip: naneng-combphy: Set rk3562 gate_tx_pck_sel length select work for L1SS

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Change-Id: I18a163b70d9387a9b8b9ca2cb24dc95780592761
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2025-03-19 15:22:14 +08:00
committed by Dingqiang Lin
parent 7ce9fd357d
commit bf69e15bdc
1 changed files with 3 additions and 0 deletions
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3
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -707,6 +707,9 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
case 100000000:
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
if (priv->mode == PHY_TYPE_PCIE) {
/* gate_tx_pck_sel length select work for L1SS */
rockchip_combphy_updatel(priv, GENMASK(7, 7), BIT(7), 0x1d << 2);
/* PLL KVCO tuning fine */
rockchip_combphy_updatel(priv, GENMASK(4, 2), 0x2 << 2, 0x20 << 2);