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arm64: dts: rockchip: rk3568: Set SDHCI core clk to 200MHz

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As we mask our SDHCI controller as SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
host->max_clk is derived from core clock in the first place. Then
f_max works together with it.

If we adjust loader's core clk setting, such as 50MHz, we will get
50MHz for host->max_clk, because .get_max_clock() reads core clk
when probing driver. That will lead f_max be set to 50MHz as well,
no matter if max-frequency is set higher than 50MHz.

We can simple solve this problem by assigning core clk as 200MHz
in the first place and then let max-frequency property takes over
it.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Idb2fdb8f68881d0286d977dc3718b74c30d3bc67
This commit is contained in:
Shawn Lin
2021-09-03 08:27:21 +08:00
committed by Tao Huang
parent 2ecea59132
commit c18fd2aea2
1 changed files with 3 additions and 2 deletions
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5
arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -2462,8 +2462,9 @@
compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
reg = <0x0 0xfe310000 0x0 0x10000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
assigned-clock-rates = <200000000>, <24000000>;
assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
<&cru CCLK_EMMC>;
assigned-clock-rates = <200000000>, <24000000>, <200000000>;
clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
<&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
<&cru TCLK_EMMC>;