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clk: rockchip: rk3576: Export CLK_AUDIO_FRAC_SRC

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Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I57d467cdba4295a78a9d2b73ff90add51eee8acf
This commit is contained in:
Sugar Zhang
2024-04-02 14:06:09 +08:00
committed by Tao Huang
parent 0f466460c8
commit c3c63e6eeb
2 changed files with 12 additions and 8 deletions
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16
drivers/clk/rockchip/clk-rk3576.c
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@@ -455,25 +455,25 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = {
COMPOSITE(ACLK_VO0VOP_CHANNEL, "aclk_vo0vop_channel", gpll_cpll_lpll_bpll_p, CLK_IS_CRITICAL,
RK3576_CLKSEL_CON(19), 12, 2, MFLAGS, 8, 4, DFLAGS,
RK3576_CLKGATE_CON(2), 1, GFLAGS),
MUX(0, "clk_audio_frac_0_src", gpll_cpll_aupll_24m_p, 0,
MUX(CLK_AUDIO_FRAC_0_SRC, "clk_audio_frac_0_src", gpll_cpll_aupll_24m_p, 0,
RK3576_CLKSEL_CON(13), 0, 2, MFLAGS),
COMPOSITE_FRAC(CLK_AUDIO_FRAC_0, "clk_audio_frac_0", "clk_audio_frac_0_src", 0,
RK3576_CLKSEL_CON(12), 0,
RK3576_CLKSEL_CON(12), CLK_FRAC_DIVIDER_NO_LIMIT,
RK3576_CLKGATE_CON(1), 10, GFLAGS),
MUX(0, "clk_audio_frac_1_src", gpll_cpll_aupll_24m_p, 0,
MUX(CLK_AUDIO_FRAC_1_SRC, "clk_audio_frac_1_src", gpll_cpll_aupll_24m_p, 0,
RK3576_CLKSEL_CON(15), 0, 2, MFLAGS),
COMPOSITE_FRAC(CLK_AUDIO_FRAC_1, "clk_audio_frac_1", "clk_audio_frac_1_src", 0,
RK3576_CLKSEL_CON(14), 0,
RK3576_CLKSEL_CON(14), CLK_FRAC_DIVIDER_NO_LIMIT,
RK3576_CLKGATE_CON(1), 11, GFLAGS),
MUX(0, "clk_audio_frac_2_src", gpll_cpll_aupll_24m_p, 0,
MUX(CLK_AUDIO_FRAC_2_SRC, "clk_audio_frac_2_src", gpll_cpll_aupll_24m_p, 0,
RK3576_CLKSEL_CON(17), 0, 2, MFLAGS),
COMPOSITE_FRAC(CLK_AUDIO_FRAC_2, "clk_audio_frac_2", "clk_audio_frac_2_src", 0,
RK3576_CLKSEL_CON(16), 0,
RK3576_CLKSEL_CON(16), CLK_FRAC_DIVIDER_NO_LIMIT,
RK3576_CLKGATE_CON(1), 12, GFLAGS),
MUX(0, "clk_audio_frac_3_src", gpll_cpll_aupll_24m_p, 0,
MUX(CLK_AUDIO_FRAC_3_SRC, "clk_audio_frac_3_src", gpll_cpll_aupll_24m_p, 0,
RK3576_CLKSEL_CON(19), 0, 2, MFLAGS),
COMPOSITE_FRAC(CLK_AUDIO_FRAC_3, "clk_audio_frac_3", "clk_audio_frac_3_src", 0,
RK3576_CLKSEL_CON(18), 0,
RK3576_CLKSEL_CON(18), CLK_FRAC_DIVIDER_NO_LIMIT,
RK3576_CLKGATE_CON(1), 13, GFLAGS),
MUX(0, "clk_uart_frac_0_src", gpll_cpll_aupll_24m_p, 0,
RK3576_CLKSEL_CON(22), 0, 2, MFLAGS),

4
include/dt-bindings/clock/rockchip,rk3576-cru.h
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@@ -553,6 +553,10 @@
#define ACLK_CRYPTO_NS 551
#define CLK_PKA_CRYPTO_NS 552
#define ACLK_RKVDEC_ROOT_BAK 553
#define CLK_AUDIO_FRAC_0_SRC 554
#define CLK_AUDIO_FRAC_1_SRC 555
#define CLK_AUDIO_FRAC_2_SRC 556
#define CLK_AUDIO_FRAC_3_SRC 557
/* secure clk */
#define CLK_STIMER0_ROOT 600