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drm/rockchip: vop2: adjust hfp and hbp for YUV420 output

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For RK3576 YUV420 output, hden signal introduce one cycle delay,
so we need to adjust hfp and hbp to compatible with this design.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I272f3e145bfe216b1d76f6313c43180040590deb
This commit is contained in:
Sandy Huang
2024-02-27 16:33:24 +08:00
committed by Tao Huang
parent bcc718e4cf
commit c4642391b1
1 changed files with 9 additions and 0 deletions
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9
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -7364,6 +7364,15 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
}
}
/*
* For RK3576 YUV420 output, hden signal introduce one cycle delay,
* so we need to adjust hfp and hbp to compatible with this design.
*/
if (vop2->version == VOP_VERSION_RK3576 && vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420) {
adj_mode->hsync_start += 2;
adj_mode->hsync_end += 2;
}
drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
if (mode->flags & DRM_MODE_FLAG_DBLCLK || vcstate->output_if & VOP_OUTPUT_IF_BT656)