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drm/rockchip: dsi: update GRF_REG_FIELD

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update this for support some GRF's register offset over 0x10000

Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: I8427e17fafa537980f2233483c23e8f3511fd9e9
This commit is contained in:
Nickey Yang
2020-03-12 15:08:27 +08:00
parent 86d27c996d
commit c4cf9286aa
1 changed files with 5 additions and 5 deletions
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10
drivers/gpu/drm/rockchip/dw-mipi-dsi.c
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@@ -213,7 +213,7 @@ enum operation_mode {
COMMAND_MODE,
};
#define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb))
#define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 10) | ((lsb) << 5) | (msb))
enum grf_reg_fields {
DPIUPDATECFG,
@@ -300,15 +300,15 @@ static void grf_field_write(struct dw_mipi_dsi *dsi, enum grf_reg_fields index,
const u32 field = dsi->id ?
dsi->pdata->dsi1_grf_reg_fields[index] :
dsi->pdata->dsi0_grf_reg_fields[index];
u16 reg;
u32 reg;
u8 msb, lsb;
if (!field)
return;
reg = (field >> 16) & 0xffff;
lsb = (field >> 8) & 0xff;
msb = (field >> 0) & 0xff;
reg = (field >> 10) & 0x3ffff;
lsb = (field >> 5) & 0x1f;
msb = (field >> 0) & 0x1f;
regmap_write(dsi->grf, reg, (val << lsb) | (GENMASK(msb, lsb) << 16));
}