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clk: rockchip: add flag CLK_GATE_NO_SET_RATE

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Add CLK_GATE_NO_SET_RATE for gate clks not allowed to support setting
rate.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Iddd1c958661f8ff9217b8781426314b0619367db
This commit is contained in:
Elaine Zhang
2021-06-07 11:30:46 +08:00
committed by Tao Huang
parent d7fb9ec48d
commit c56568e8bf
2 changed files with 5 additions and 1 deletions
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3
drivers/clk/rockchip/clk.c
View File

@@ -618,7 +618,8 @@ void __init rockchip_clk_register_branches(
flags, &ctx->lock);
break;
case branch_gate:
flags |= CLK_SET_RATE_PARENT;
if (!(list->gate_flags & CLK_GATE_NO_SET_RATE))
flags |= CLK_SET_RATE_PARENT;
clk = clk_register_gate(NULL, list->name,
list->parent_names[0], flags,

3
include/linux/clk-provider.h
View File

@@ -445,6 +445,8 @@ void of_fixed_clk_setup(struct device_node *np);
* of this register, and mask of gate bits are in higher 16-bit of this
* register. While setting the gate bits, higher 16-bit should also be
* updated to indicate changing gate bits.
* CLK_GATE_NO_SET_RATE - The Gate not allowed to set rate.
* And not allowed to set parent rate.
*/
struct clk_gate {
struct clk_hw hw;
@@ -458,6 +460,7 @@ struct clk_gate {
#define CLK_GATE_SET_TO_DISABLE BIT(0)
#define CLK_GATE_HIWORD_MASK BIT(1)
#define CLK_GATE_NO_SET_RATE BIT(3)
extern const struct clk_ops clk_gate_ops;
struct clk *clk_register_gate(struct device *dev, const char *name,