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clk: rockchip: rk3368: use COMPOSITE_DCLK for dclk_vop

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Change-Id: I45ce9a2e404acb7eae885fbca0b4703ec67176e9
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2020-05-06 09:46:22 +08:00
committed by Tao Huang
parent 2145f9dccb
commit c86aa0a6b3
1 changed files with 3 additions and 2 deletions
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5
drivers/clk/rockchip/clk-rk3368.c
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@@ -15,6 +15,7 @@
#define RK3368_I2S_FRAC_MAX_PRATE 600000000
#define RK3368_UART_FRAC_MAX_PRATE 600000000
#define RK3368_SPDIF_FRAC_MAX_PRATE 600000000
#define RK3368_DCLK_PARENT_MAX_PRATE 600000000
enum rk3368_plls {
apllb, aplll, dpll, cpll, gpll, npll,
@@ -469,9 +470,9 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(4), 4, GFLAGS),
COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_dmycpll_dmygpll_npll_p, CLK_SET_RATE_PARENT,
COMPOSITE_DCLK(DCLK_VOP, "dclk_vop", mux_pll_src_dmycpll_dmygpll_npll_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3368_CLKGATE_CON(4), 1, GFLAGS),
RK3368_CLKGATE_CON(4), 1, GFLAGS, RK3368_DCLK_PARENT_MAX_PRATE),
GATE(SCLK_VOP0_PWM, "sclk_vop0_pwm", "xin24m", 0,
RK3368_CLKGATE_CON(4), 2, GFLAGS),