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phy: rockchip: naneng-combphy: Force to select mode from GRF for SGMII/QSGMII

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Because phy1 is sata mode by default, and phy2 is pcie mode by default, when using qsgmii on phy1, it needs to be configured as pcie mode, because pcie mode is compatible with K28.1 and K28.5, while sata only has K28.5. If phy1 is in sata mode, qsgmii will not work, and both K codes need to be used at the same time. Based on this, we unified configuration into pcie mode.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I4a9e5a2cdcee448ec3457778bf4ee7135be70087
This commit is contained in:
David Wu
2021-02-22 16:39:26 +08:00
committed by Tao Huang
parent a2e043603e
commit cabce2b042
1 changed files with 4 additions and 0 deletions
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4
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -40,6 +40,7 @@ struct rockchip_combphy_grfcfg {
struct combphy_reg pipe_txcomp_set;
struct combphy_reg pipe_clk_25m;
struct combphy_reg pipe_clk_100m;
struct combphy_reg pipe_phymode_sel;
struct combphy_reg pipe_rate_sel;
struct combphy_reg pipe_rxterm_sel;
struct combphy_reg pipe_txelec_sel;
@@ -463,11 +464,13 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
break;
case PHY_TYPE_SGMII:
param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
break;
case PHY_TYPE_QSGMII:
param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
@@ -557,6 +560,7 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
.pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
.pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
.pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
.pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
.pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
.pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
.pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },