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drm/rockchip: vop2: add support mipi dsi cmd mode panel

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for vp2/vp3, we can use hardware or software TE to sync with panel ram,
but for vp1->dsc1->dsc1 path, we only can use software TE to sync with panel
ram.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I0f54723c5c1c45916e669ce21819a127dc5b415d
This commit is contained in:
Sandy Huang
2021-12-01 11:28:11 +08:00
committed by Tao Huang
parent be1e4b616a
commit cc5f5c07a0
3 changed files with 40 additions and 0 deletions
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4
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -697,6 +697,10 @@ struct vop2_video_port_regs {
struct vop_reg dclk_src_sel;
struct vop_reg splice_en;
struct vop_reg edpi_wms_hold_en;
struct vop_reg edpi_te_en;
struct vop_reg edpi_wms_fs;
};
struct vop2_power_domain_regs {

24
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -4934,6 +4934,17 @@ static void vop2_crtc_close(struct drm_crtc *crtc)
mutex_unlock(&vop2->vop2_lock);
}
static void vop2_crtc_te_handler(struct drm_crtc *crtc)
{
struct vop2_video_port *vp = to_vop2_video_port(crtc);
struct vop2 *vop2 = vp->vop2;
if (!crtc || !crtc->state->active)
return;
VOP_MODULE_SET(vop2, vp, edpi_wms_fs, 1);
}
static const struct rockchip_crtc_funcs private_crtc_funcs = {
.loader_protect = vop2_crtc_loader_protect,
.cancel_pending_vblank = vop2_crtc_cancel_pending_vblank,
@@ -4942,6 +4953,7 @@ static const struct rockchip_crtc_funcs private_crtc_funcs = {
.regs_dump = vop2_crtc_regs_dump,
.bandwidth = vop2_crtc_bandwidth,
.crtc_close = vop2_crtc_close,
.te_handler = vop2_crtc_te_handler,
};
static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
@@ -5776,6 +5788,10 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
VOP_CTRL_SET(vop2, mipi0_mux, port_mux);
VOP_CTRL_SET(vop2, mipi_pin_pol, val);
VOP_CTRL_SET(vop2, mipi_dclk_pol, dclk_inv);
if (vcstate->hold_mode) {
VOP_MODULE_SET(vop2, vp, edpi_te_en, 1);
VOP_MODULE_SET(vop2, vp, edpi_wms_hold_en, 1);
}
}
if (vcstate->output_if & VOP_OUTPUT_IF_MIPI1) {
@@ -5794,6 +5810,14 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
VOP_CTRL_SET(vop2, mipi1_mux, port_mux);
VOP_CTRL_SET(vop2, mipi_pin_pol, val);
VOP_CTRL_SET(vop2, mipi_dclk_pol, dclk_inv);
if (vcstate->hold_mode) {
/* RK3588 VP1->DSC1->DSI1 only can support soft TE mode */
if (vop2->version == VOP_VERSION_RK3588 && vp->id == 1)
VOP_MODULE_SET(vop2, vp, edpi_te_en, 0);
else
VOP_MODULE_SET(vop2, vp, edpi_te_en, 1);
VOP_MODULE_SET(vop2, vp, edpi_wms_hold_en, 1);
}
}
if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)

12
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -927,6 +927,9 @@ static const struct vop2_video_port_regs rk3588_vop_vp0_regs = {
.bcsh_y2r_csc_mode = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x3, 2),
.bcsh_y2r_en = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x1, 0),
.bcsh_en = VOP_REG(RK3568_VP0_BCSH_COLOR_BAR, 0x1, 31),
.edpi_te_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 28),
.edpi_wms_hold_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 30),
.edpi_wms_fs = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 31),
};
/*
@@ -1009,6 +1012,9 @@ static const struct vop2_video_port_regs rk3588_vop_vp1_regs = {
.bcsh_y2r_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 2),
.bcsh_y2r_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 0),
.bcsh_en = VOP_REG(RK3568_VP1_BCSH_COLOR_BAR, 0x1, 31),
.edpi_te_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 28),
.edpi_wms_hold_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 30),
.edpi_wms_fs = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 31),
};
static const struct vop2_video_port_regs rk3588_vop_vp2_regs = {
@@ -1057,6 +1063,9 @@ static const struct vop2_video_port_regs rk3588_vop_vp2_regs = {
.bcsh_y2r_csc_mode = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x3, 2),
.bcsh_y2r_en = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x1, 0),
.bcsh_en = VOP_REG(RK3568_VP2_BCSH_COLOR_BAR, 0x1, 31),
.edpi_te_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 28),
.edpi_wms_hold_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 30),
.edpi_wms_fs = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 31),
};
static const struct vop2_video_port_regs rk3588_vop_vp3_regs = {
@@ -1105,6 +1114,9 @@ static const struct vop2_video_port_regs rk3588_vop_vp3_regs = {
.bcsh_y2r_csc_mode = VOP_REG(RK3588_VP3_BCSH_CTRL, 0x3, 2),
.bcsh_y2r_en = VOP_REG(RK3588_VP3_BCSH_CTRL, 0x1, 0),
.bcsh_en = VOP_REG(RK3588_VP3_BCSH_COLOR_BAR, 0x1, 31),
.edpi_te_en = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 28),
.edpi_wms_hold_en = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 30),
.edpi_wms_fs = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 31),
};
static const struct vop2_video_port_data rk3588_vop_video_ports[] = {