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ARM: dts: rv1126: isp and ispp add iommu and domain

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Change-Id: I1fb85c6ec6462745893a2b26154bb37f0e8e8d2e
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
Cai YiWei
2020-03-19 17:12:28 +08:00
committed by Tao Huang
parent fe0393d949
commit ccb79e4fd2
1 changed files with 32 additions and 0 deletions
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32
arch/arm/boot/dts/rv1126.dtsi
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@@ -1234,6 +1234,21 @@
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
<&cru CLK_ISP>;
clock-names = "aclk_isp", "hclk_isp", "clk_isp";
power-domains = <&power RV1126_PD_VI>;
iommus = <&rkisp_mmu>;
status = "disabled";
};
rkisp_mmu: iommu@ffb51a00 {
compatible = "rockchip,iommu";
reg = <0xffb51a00 0x100>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "isp_mmu";
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
clock-names = "aclk", "iface";
power-domains = <&power RV1126_PD_VI>;
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
status = "disabled";
};
@@ -1246,6 +1261,23 @@
clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>,
<&cru CLK_ISPP>;
clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
power-domains = <&power RV1126_PD_ISPP>;
iommus = <&rkispp_mmu>;
status = "disabled";
};
rkispp_mmu: iommu@ffb60e00 {
compatible = "rockchip,iommu";
reg = <0xffb60e00 0x40>, <0xffb60e40 0x40>, <0xffb60f00 0x40>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ispp_mmu0_r", "ispp_mmu0_w", "ispp_mmu1";
clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>;
clock-names = "aclk", "iface";
power-domains = <&power RV1126_PD_ISPP>;
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
status = "disabled";
};