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clk: rockchip: rk3308: Set max parent rate for vop fractional divider

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Change-Id: I79b5b412e2952d48e83546dce69c6ce2fbe75e5b
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2018-03-28 20:04:58 +08:00
committed by Tao Huang
parent 0689ad72e4
commit cd5289db24
1 changed files with 2 additions and 1 deletions
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3
drivers/clk/rockchip/clk-rk3308.c
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@@ -21,6 +21,7 @@
#include "clk.h"
#define RK3308_GRF_SOC_STATUS0 0x380
#define RK3308_VOP_FRAC_MAX_PRATE 270000000
enum rk3308_plls {
apll, dpll, vpll0, vpll1,
@@ -454,7 +455,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(9), 0,
RK3308_CLKGATE_CON(1), 7, GFLAGS,
&rk3308_dclk_vop_fracmux, 0),
&rk3308_dclk_vop_fracmux, RK3308_VOP_FRAC_MAX_PRATE),
GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
RK3308_CLKGATE_CON(1), 8, GFLAGS),