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drm/rockchip: dsi2: config cphy lp2hs/hs2lp timing

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Change-Id: I37edc1aabc5592b2ab6453ea2bf966e82809947a
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
This commit is contained in:
Guochun Huang
2021-11-22 11:33:39 +00:00
committed by Tao Huang
parent b46d142d92
commit d08def6b42
1 changed files with 3 additions and 6 deletions
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9
drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
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@@ -450,13 +450,14 @@ static void dw_mipi_dsi2_encoder_disable(struct drm_encoder *encoder)
{
struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
dw_mipi_dsi2_irq_enable(dsi2, 0);
if (dsi2->panel)
drm_panel_disable(dsi2->panel);
dw_mipi_dsi2_disable(dsi2);
if (dsi2->panel)
drm_panel_unprepare(dsi2->panel);
dw_mipi_dsi2_post_disable(dsi2);
}
@@ -592,10 +593,6 @@ static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2)
unsigned long long tmp, ui;
unsigned long long hstx_clk;
/* test dphy firstly */
if (dsi2->c_option)
return;
hstx_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * USEC_PER_SEC, 16);
ui = ALIGN(PSEC_PER_SEC, hstx_clk);