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phy/rockchip: samsung-hdptx: Optimize reset sequence to save power

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Signed-off-by: Wyon bi <bivvy.bi@rock-chips.com>
Change-Id: I5438bb7b21ea88c305545c2ac42010cee6cfa639
This commit is contained in:
Wyon bi
2021-12-25 16:31:34 +08:00
committed by Tao Huang
parent ab65fe5bce
commit d0900b6f0a
1 changed files with 17 additions and 5 deletions
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22
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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@@ -186,6 +186,7 @@
/* sb_reg010F */
#define OVRD_SB_VREG_EN BIT(7)
#define SB_VREG_EN BIT(6)
#define ANA_SB_VREG_GAIN_CTRL GENMASK(3, 0)
/* sb_reg0110 */
@@ -193,7 +194,6 @@
#define ANA_SB_VREG_REF_SEL BIT(0)
/* sb_reg0113 */
#define SB_VREG_EN BIT(6)
#define SB_RX_RCAL_OPT_CODE GENMASK(5, 4)
#define SB_RX_RTERM_CTRL GENMASK(3, 0)
@@ -251,6 +251,10 @@
/* lntop_reg0207 */
#define LANE_EN GENMASK(3, 0)
/* lane_reg0301 */
#define OVRD_LN_TX_DRV_EI_EN BIT(7)
#define LN_TX_DRV_EI_EN BIT(6)
/* lane_reg0303 */
#define OVRD_LN_TX_DRV_LVL_CTRL BIT(5)
#define LN_TX_DRV_LVL_CTRL GENMASK(4, 0)
@@ -874,10 +878,22 @@ static int rockchip_hdptx_phy_dp_aux_init(struct rockchip_hdptx_phy *hdptx)
static void rockchip_hdptx_phy_reset(struct rockchip_hdptx_phy *hdptx)
{
u32 lane;
reset_control_assert(hdptx->lane_reset);
reset_control_assert(hdptx->cmn_reset);
reset_control_assert(hdptx->init_reset);
reset_control_assert(hdptx->apb_reset);
udelay(10);
reset_control_deassert(hdptx->apb_reset);
for (lane = 0; lane < 4; lane++)
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c04),
OVRD_LN_TX_DRV_EI_EN | LN_TX_DRV_EI_EN,
FIELD_PREP(OVRD_LN_TX_DRV_EI_EN, 1) |
FIELD_PREP(LN_TX_DRV_EI_EN, 0));
rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN,
FIELD_PREP(PLL_EN, 0));
rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BIAS_EN,
@@ -911,10 +927,6 @@ static int rockchip_hdptx_phy_power_on(struct phy *phy)
rockchip_hdptx_phy_reset(hdptx);
reset_control_assert(hdptx->apb_reset);
udelay(10);
reset_control_deassert(hdptx->apb_reset);
for (lane = 0; lane < 4; lane++) {
u32 invert = hdptx->lane_polarity_invert[lane];