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drm/rockchip/rk628: combtxphy: ref_clk should not be zero
Change-Id: I395d721b2ab833fee6dfbdb53c6fc923f733a3d1 Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
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@@ -366,6 +366,10 @@ static int rk628_combtxphy_set_mode(struct phy *phy, enum phy_mode mode,
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ref_clk = clk_get_rate(combtxphy->ref_clk) / 1000; /* khz */
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if (combtxphy->division_mode)
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ref_clk /= 2;
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if (!ref_clk)
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return -EINVAL;
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/*
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* the reference clock at PFD(FPFD = ref_clk / ref_div) about
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* 25MHz is recommende, FPFD must range from 16MHz to 35MHz,
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