drm/rockchip/rk628: combtxphy: ref_clk should not be zero

Change-Id: I395d721b2ab833fee6dfbdb53c6fc923f733a3d1
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
This commit is contained in:
Guochun Huang
2023-11-13 11:33:37 +00:00
committed by Tao Huang
parent c952ca6f8c
commit d090ed8f63

View File

@@ -366,6 +366,10 @@ static int rk628_combtxphy_set_mode(struct phy *phy, enum phy_mode mode,
ref_clk = clk_get_rate(combtxphy->ref_clk) / 1000; /* khz */
if (combtxphy->division_mode)
ref_clk /= 2;
if (!ref_clk)
return -EINVAL;
/*
* the reference clock at PFD(FPFD = ref_clk / ref_div) about
* 25MHz is recommende, FPFD must range from 16MHz to 35MHz,