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drm/rockchip: dsi: Fix improved D-PHY data lanes timing

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Change-Id: Ibc8dfd6bf208407117156dc36539d95740b213d8
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2019-07-09 17:50:45 +08:00
parent 8f2cf6a08d
commit d13ab488bb
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/rockchip/dw-mipi-dsi.c
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@@ -997,8 +997,8 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
{
regmap_write(dsi->regmap, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) |
PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
regmap_write(dsi->regmap, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14) |
PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000));
regmap_write(dsi->regmap, DSI_PHY_TMR_LPCLK_CFG,
PHY_CLKHS2LP_TIME(0x40) | PHY_CLKLP2HS_TIME(0x40));