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ARM: dts: rockchip: rk3506: add osc clk configs for pwm0

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For rk3506, pwm0 supports wave generator mode, which
relies on the osc clk.

Change-Id: I8897595eeda31b0f606c2f2f6a365a1125fceeac
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
This commit is contained in:
Damon Ding
2024-07-23 17:27:52 +08:00
committed by Tao Huang
parent 19b3f8d830
commit d28c2096be
1 changed files with 8 additions and 8 deletions
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16
arch/arm/boot/dts/rk3506.dtsi
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@@ -1592,8 +1592,8 @@
compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
reg = <0xff930000 0x200>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>;
clock-names = "pwm", "pclk", "osc";
#pwm-cells = <3>;
status = "disabled";
};
@@ -1602,8 +1602,8 @@
compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
reg = <0xff931000 0x200>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>;
clock-names = "pwm", "pclk", "osc";
#pwm-cells = <3>;
status = "disabled";
};
@@ -1612,8 +1612,8 @@
compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
reg = <0xff932000 0x200>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>;
clock-names = "pwm", "pclk", "osc";
#pwm-cells = <3>;
status = "disabled";
};
@@ -1622,8 +1622,8 @@
compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
reg = <0xff933000 0x200>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>, <&cru CLK_OSC_PWM0>;
clock-names = "pwm", "pclk", "osc";
#pwm-cells = <3>;
status = "disabled";
};