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phy: rockchip-inno-combphy: tuning lane 0 TX driver swing for usb

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This patch tuning lane 0 TX driver swing for USB 3.0 to
get larger swing for LFPS.

Test on RK1808-stick board:
offset[0x21b8]  5G LFPS Peak-Peak Differential Output Voltage
     0xd9            Actual Value: 807.9mv Margin: 2.0%
     0xe9            Actual Value: 832.2mv Margin: 8.1%
     0xf9            Actual Value: 842.7mv Margin: 10.7%

We set PHY register offset[0x21b8] to 0xe9 in this patch.

Change-Id: Ic1878fbea5c0b67ce943544e9d9afdf912341b45
Signed-off-by: William Wu <william.wu@rock-chips.com>
This commit is contained in:
William Wu
2019-05-30 15:59:41 +08:00
parent c4a6c7275d
commit d3528bf2ff
1 changed files with 1 additions and 1 deletions
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2
drivers/phy/rockchip/phy-rockchip-inno-combphy.c
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@@ -889,7 +889,7 @@ static int rk1808_combphy_cfg(struct rockchip_combphy_priv *priv)
* largest swing and "0000" the smallest.
*/
reg = readl(priv->mmio + 0x21b8);
reg = (reg & ~0xf0) | 0xa0;
reg = (reg & ~0xf0) | 0xe0;
writel(reg, priv->mmio + 0x21b8);
/*