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PCI: rockchip: dw: decrease linking timeout to 10s

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The original waiting time is too long for setting up a link, so
let's decrease it to 10s which is enough for real usecase.

Change-Id: Ifb1eb0d7784e9afeef165f084bc3bda49b41618e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This commit is contained in:
Shawn Lin
2020-12-09 10:28:20 +08:00
committed by Tao Huang
parent 2af29f5de3
commit d38988a104
1 changed files with 2 additions and 2 deletions
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4
drivers/pci/controller/dwc/pcie-dw-rockchip.c
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@@ -451,7 +451,7 @@ static int rk_pcie_establish_link(struct dw_pcie *pci)
/* Enable LTSSM */
rk_pcie_enable_ltssm(rk_pcie);
for (retries = 0; retries < 1000000; retries++) {
for (retries = 0; retries < 10; retries++) {
if (dw_pcie_link_up(pci)) {
dev_info(pci->dev, "PCIe Link up, LTSSM is 0x%x\n",
rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
@@ -462,7 +462,7 @@ static int rk_pcie_establish_link(struct dw_pcie *pci)
dev_info_ratelimited(pci->dev, "PCIe Linking... LTSSM is 0x%x\n",
rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
rk_pcie_debug_dump(rk_pcie);
mdelay(1000);
msleep(1000);
}
dev_err(pci->dev, "PCIe Link Fail\n");