media: adds the register ops for media codec io efuse bus [1/2].

PD#161104: adds the register ops for media codec io efuse bus

Change-Id: I6fc625848442754b089428fd8cb10a3047fa4062
Signed-off-by: Nanxin Qin <nanxin.qin@amlogic.com>

MAINTAINERS

@@ -14375,3 +14375,7 @@ AMLOGIC G12A Dolby Vision DRIVER
 M:	Zhilei Wu <zhilei.wu@amlogic.com>
 F:	drivers/amlogic/media/enhancement/amdolby_vision*
 F:	include/linux/amlogic/media/amdolbyvision/*
+
+AMLOGIC G12A Media codec io bus
+M:	Nanxin Qin <nanxin.qin@amlogic.com>
+F:	include/linux/amlogic/media/registers/regs/efuse_regs.h

arch/arm64/boot/dts/amlogic/g12a_skt.dts

@@ -610,6 +610,9 @@
 		io_dmc_base{
 			reg = <0x0 0xff638000 0x0 0x2000>;
 		};
+		io_efuse_base{
+			reg = <0x0 0xff630000 0x0 0x2000>;
+		};
 	};
 
 	codec_mm {

drivers/amlogic/media/common/arch/registers/register_map.c

@@ -45,6 +45,7 @@ enum {
 	CODECIO_AOBUS_BASE,
 	CODECIO_VCBUS_BASE,
 	CODECIO_DMCBUS_BASE,
+	CODECIO_EFUSE_BASE,
 	CODECIO_BUS_MAX,
 };
 
@@ -311,6 +312,28 @@ void codecio_write_resetbus(unsigned int reg, unsigned int val)
 		pr_err("write reset reg %x error %d\n", reg, ret);
 }
 
+int codecio_read_efusebus(unsigned int reg)
+{
+	int ret, val;
+
+	ret = codecio_reg_read(CODECIO_EFUSE_BASE, reg << 2, &val);
+	if (ret) {
+		pr_err("read reset reg %x error %d\n", reg, ret);
+		return -1;
+	}
+
+	return val;
+}
+
+void codecio_write_efusebus(unsigned int reg, unsigned int val)
+{
+	int ret;
+
+	ret = codecio_reg_write(CODECIO_EFUSE_BASE, reg << 2, val);
+	if (ret)
+		pr_err("write reset reg %x error %d\n", reg, ret);
+}
+
 static int codec_io_probe(struct platform_device *pdev)
 {
 	int i = 0;

drivers/amlogic/media/common/arch/registers/register_ops_m8.c

@@ -65,6 +65,7 @@ static struct chip_register_ops m8_ops[] __initdata = {
 	{IO_AIU_BUS, 0, codecio_read_aiubus, codecio_write_aiubus},
 	{IO_DEMUX_BUS, 0, codecio_read_demuxbus, codecio_write_demuxbus},
 	{IO_RESET_BUS, 0, codecio_read_resetbus, codecio_write_resetbus},
+	{IO_EFUSE_BUS, 0, codecio_read_efusebus, codecio_write_efusebus},
 };
 
 static struct chip_register_ops ex_gx_ops[] __initdata = {

include/linux/amlogic/media/registers/register.h

@@ -39,5 +39,6 @@
 #include "regs/demux_regs.h"
 #include "regs/ao_regs.h"
 #include "regs/dmc_regs.h"
+#include "regs/efuse_regs.h"
 
 #endif

include/linux/amlogic/media/registers/register_map.h

@@ -37,4 +37,6 @@ int codecio_read_demuxbus(unsigned int reg);
 void codecio_write_demuxbus(unsigned int reg, unsigned int val);
 int codecio_read_resetbus(unsigned int reg);
 void codecio_write_resetbus(unsigned int reg, unsigned int val);
+int codecio_read_efusebus(unsigned int reg);
+void codecio_write_efusebus(unsigned int reg, unsigned int val);
 #endif

include/linux/amlogic/media/registers/register_ops.h

@@ -43,6 +43,7 @@ enum
 	IO_VPP_BUS,
 	IO_DMC_BUS,
 	IO_RESET_BUS,
+	IO_EFUSE_BUS,
 	BUS_MAX
 };
 
@@ -67,6 +68,7 @@ int register_reg_ops_mgr(int cputype[], struct chip_register_ops *sops_list,
 	int ops_size);
 int register_reg_ex_ops_mgr(int cputype[],
 	struct chip_register_ops *ex_ops_list, int ops_size);
+
 #define DEF_BUS_OPS(BUS_TYPE, name)\
 static inline void codec_##name##bus_write(unsigned int reg, u32 val)\
 {\
@@ -113,5 +115,6 @@ DEF_BUS_OPS(IO_PARSER_BUS, pars);
 DEF_BUS_OPS(IO_AIU_BUS, aiu);
 DEF_BUS_OPS(IO_DEMUX_BUS, demux);
 DEF_BUS_OPS(IO_RESET_BUS, reset);
+DEF_BUS_OPS(IO_EFUSE_BUS, efuse);
 
 #endif

include/linux/amlogic/media/registers/regs/efuse_regs.h

@@ -0,0 +1,37 @@
+/*
+ * include/linux/amlogic/media/registers/regs/efuse_regs.h
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef EFUSE_REGS_HEADER_
+#define EFUSE_REGS_HEADER_
+
+#define	EFUSE_CLR	(0x0)
+#define	EFUSE_START	(0x1)
+#define	EFUSE_WDATA0	(0x4)
+#define	EFUSE_WDATA1	(0x5)
+#define	EFUSE_WDATA2	(0x6)
+#define	EFUSE_WDATA3	(0x7)
+#define	EFUSE_RDATA0	(0x8)
+#define	EFUSE_RDATA1	(0x9)
+#define	EFUSE_RDATA2	(0xa)
+#define	EFUSE_RDATA3	(0xb)
+#define	EFUSE_LIC0	(0xc)
+#define	EFUSE_LIC1	(0xd)
+#define	EFUSE_LIC2	(0xe)
+#define	EFUSE_LIC3	(0xf)
+
+#endif
+

include/linux/amlogic/media/registers/regs/hevc_regs.h

@@ -304,8 +304,8 @@
 #define HEVC_DBLK_CFG9 0x3509
 #define HEVC_DBLK_CFGA 0x350a
 #define HEVC_DBLK_CFGE 0x350e
-#define HEVC_DBLK_STS0 0x350b
-#define HEVC_DBLK_STS1 0x350c
+#define HEVC_DBLK_STS0 0x350b	/* changes the val to 0x350f on g12a */
+#define HEVC_DBLK_STS1 0x350c	/* changes the val to 0x3510 on g12a */
 #define HEVC_SAO_VERSION 0x3600
 #define HEVC_SAO_CTRL0 0x3601
 #define HEVC_SAO_CTRL1 0x3602

include/linux/amlogic/media/utils/vdec_reg.h

@@ -175,6 +175,17 @@
 #define SET_RESET_REG_MASK(r, mask)\
 	WRITE_RESET_REG(r, READ_RESET_REG(r) | (mask))
 
+#define WRITE_EFUSE_REG(r, val) codec_efusebus_write(r, val)
+#define READ_EFUSE_REG(r) codec_efusebus_read(r)
+#define WRITE_EFUSE_REG_BITS(r, val, start, len) \
+	WRITE_EFUSE_REG(r, (READ_EFUSE_REG(r) & ~(((1L<<(len))-1)<<(start)))|\
+		    ((unsigned int)((val)&((1L<<(len))-1)) << (start)))
+
+#define CLEAR_EFUSE_REG_MASK(r, mask)\
+	WRITE_EFUSE_REG(r, READ_EFUSE_REG(r) & ~(mask))
+#define SET_EFUSE_REG_MASK(r, mask)\
+	WRITE_EFUSE_REG(r, READ_EFUSE_REG(r) | (mask))
+
 #define ASSIST_MBOX1_CLR_REG VDEC_ASSIST_MBOX1_CLR_REG
 #define ASSIST_MBOX1_MASK VDEC_ASSIST_MBOX1_MASK
 #define ASSIST_AMR1_INT0 VDEC_ASSIST_AMR1_INT0