mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-06 02:50:49 +09:00
media: rockchip: isp: aiisp for isp35
Change-Id: I52313925f5007b9192402e50a985e8cbd42b1e73 Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
Cai YiWei
@@ -961,7 +961,7 @@ static int mi_frame_end(struct rkisp_stream *stream, u32 state)
|
||||
vb2_set_plane_payload(vb2_buf, i, payload_size);
|
||||
}
|
||||
|
||||
rkisp_dmarx_get_frame(dev, &i, NULL, &ns, true);
|
||||
rkisp_dmarx_get_frame(dev, &i, NULL, &ns, !dev->is_aiisp_en);
|
||||
if (!ns)
|
||||
ns = rkisp_time_get_ns(dev);
|
||||
buf->vb.sequence = i;
|
||||
@@ -1024,7 +1024,9 @@ static void rkisp_stream_stop(struct rkisp_stream *stream)
|
||||
stream->ops->disable_mi(stream);
|
||||
if (IS_HDR_RDBK(dev->rd_mode)) {
|
||||
spin_lock_irqsave(&dev->hw_dev->rdbk_lock, lock_flags);
|
||||
if (dev->hw_dev->cur_dev_id != dev->dev_id || dev->hw_dev->is_idle) {
|
||||
if (dev->hw_dev->cur_dev_id != dev->dev_id ||
|
||||
(!dev->is_aiisp_en && dev->hw_dev->is_idle) ||
|
||||
(dev->is_aiisp_en && dev->hw_dev->is_be_idle)) {
|
||||
is_wait = false;
|
||||
if (stream->ops->disable_mi)
|
||||
stream->ops->disable_mi(stream);
|
||||
@@ -1635,7 +1637,7 @@ void rkisp_mi_v35_isr(u32 mis_val, struct rkisp_device *dev)
|
||||
ns = rkisp_time_get_ns(dev);
|
||||
stream->dbg.interval = ns - stream->dbg.timestamp;
|
||||
stream->dbg.timestamp = ns;
|
||||
rkisp_dmarx_get_frame(dev, &seq, NULL, &ns, true);
|
||||
rkisp_dmarx_get_frame(dev, &seq, NULL, &ns, !dev->is_aiisp_en);
|
||||
stream->dbg.delay = stream->dbg.timestamp - ns;
|
||||
stream->dbg.id = seq;
|
||||
} else {
|
||||
|
||||
@@ -351,7 +351,8 @@ static int rkisp_pipeline_open(struct rkisp_pipeline *p,
|
||||
rkisp_csi_config_patch(dev, false);
|
||||
dev->is_aiisp_sync = false;
|
||||
if (dev->is_aiisp_en &&
|
||||
(dev->isp_inp & (INP_RAWRD0 | INP_RAWRD2) || dev->is_rdbk_auto))
|
||||
((dev->isp_ver == ISP_V35 && !hw->is_single) ||
|
||||
(dev->isp_ver == ISP_V39 && (dev->isp_inp & INP_RAWRD2 || dev->is_rdbk_auto))))
|
||||
dev->is_aiisp_sync = true;
|
||||
return 0;
|
||||
err:
|
||||
@@ -937,6 +938,11 @@ static int rkisp_plat_probe(struct platform_device *pdev)
|
||||
isp_dev->sw_base_addr = devm_kzalloc(dev, RKISP_ISP_SW_MAX_SIZE * mult, GFP_KERNEL);
|
||||
if (!isp_dev->sw_base_addr)
|
||||
return -ENOMEM;
|
||||
if (isp_dev->hw_dev->isp_ver == ISP_V35) {
|
||||
isp_dev->sw_vpsl_base_addr = devm_kzalloc(dev, VPSL_SW_MAX_SIZE * mult, GFP_KERNEL);
|
||||
if (!isp_dev->sw_vpsl_base_addr)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = rkisp_vs_irq_parse(dev);
|
||||
if (ret)
|
||||
|
||||
@@ -80,6 +80,7 @@ enum rkisp_isp_state {
|
||||
ISP_FRAME_BP = BIT(6),
|
||||
ISP_FRAME_LDC = BIT(7),
|
||||
ISP_FRAME_VPSS = BIT(8),
|
||||
ISP_FRAME_VPSL = BIT(9),
|
||||
|
||||
ISP_STOP = BIT(16),
|
||||
ISP_START = BIT(17),
|
||||
@@ -213,6 +214,7 @@ struct rkisp_device {
|
||||
struct device *dev;
|
||||
char name[128];
|
||||
void *sw_base_addr;
|
||||
void *sw_vpsl_base_addr;
|
||||
struct rkisp_hw_dev *hw_dev;
|
||||
struct v4l2_device v4l2_dev;
|
||||
struct v4l2_ctrl_handler ctrl_handler;
|
||||
|
||||
@@ -24,6 +24,7 @@
|
||||
#include "dev.h"
|
||||
#include "hw.h"
|
||||
#include "regs.h"
|
||||
#include "vpsl_reg.h"
|
||||
|
||||
/*
|
||||
* rkisp_hw share hardware resource with rkisp virtual device
|
||||
@@ -249,6 +250,42 @@ static irqreturn_t isp_irq_hdl(int irq, void *ctx)
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t vpsl_mi_irq_hdl(int irq, void *ctx)
|
||||
{
|
||||
struct device *dev = ctx;
|
||||
struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
|
||||
struct rkisp_device *isp = hw_dev->isp[hw_dev->cur_dev_id];
|
||||
void __iomem *base = hw_dev->vpsl_base_addr;
|
||||
u32 mis_val;
|
||||
|
||||
mis_val = readl(base + VPSL_MI_MIS);
|
||||
if (mis_val) {
|
||||
writel(mis_val, base + VPSL_MI_ICR);
|
||||
v4l2_dbg(3, rkisp_debug, &isp->v4l2_dev,
|
||||
"%s isr:0x%x\n", __func__, mis_val);
|
||||
rkisp_vpsl_mi_isr(isp, mis_val);
|
||||
}
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t vpsl_irq_hdl(int irq, void *ctx)
|
||||
{
|
||||
struct device *dev = ctx;
|
||||
struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
|
||||
struct rkisp_device *isp = hw_dev->isp[hw_dev->cur_dev_id];
|
||||
void __iomem *base = hw_dev->vpsl_base_addr;
|
||||
u32 mis_val;
|
||||
|
||||
mis_val = readl(base + VPSL_MIS);
|
||||
if (mis_val) {
|
||||
writel(mis_val, base + VPSL_ICR);
|
||||
v4l2_dbg(3, rkisp_debug, &isp->v4l2_dev,
|
||||
"%s isr:0x%x\n", __func__, mis_val);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
int rkisp_register_irq(struct rkisp_hw_dev *hw_dev)
|
||||
{
|
||||
const struct isp_match_data *match_data = hw_dev->match_data;
|
||||
@@ -794,6 +831,14 @@ static struct isp_irqs_data isp_irqs[] = {
|
||||
{"mipi_irq", mipi_irq_hdl}
|
||||
};
|
||||
|
||||
static struct isp_irqs_data isp35_irqs[] = {
|
||||
{"isp_irq", isp_irq_hdl},
|
||||
{"isp_mi_irq", mi_irq_hdl},
|
||||
{"isp_mipi_irq", mipi_irq_hdl},
|
||||
{"vpsl_mi_irq", vpsl_mi_irq_hdl},
|
||||
{"vpsl_irq", vpsl_irq_hdl},
|
||||
};
|
||||
|
||||
static const struct isp_match_data rv1103b_isp_match_data = {
|
||||
.clks = rv1106_isp_clks,
|
||||
.num_clks = ARRAY_SIZE(rv1106_isp_clks),
|
||||
@@ -833,8 +878,8 @@ static const struct isp_match_data rv1126b_isp_match_data = {
|
||||
.isp_ver = ISP_V35,
|
||||
.clk_rate_tbl = rv1126_isp_clk_rate,
|
||||
.num_clk_rate_tbl = ARRAY_SIZE(rv1126_isp_clk_rate),
|
||||
.irqs = isp_irqs,
|
||||
.num_irqs = ARRAY_SIZE(isp_irqs),
|
||||
.irqs = isp35_irqs,
|
||||
.num_irqs = ARRAY_SIZE(isp35_irqs),
|
||||
.unite = false,
|
||||
};
|
||||
|
||||
@@ -1299,6 +1344,29 @@ static int rkisp_hw_probe(struct platform_device *pdev)
|
||||
hw_dev->unite = ISP_UNITE_NONE;
|
||||
}
|
||||
|
||||
hw_dev->vpsl_base_addr = NULL;
|
||||
if (hw_dev->isp_ver == ISP_V35) {
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
if (!res) {
|
||||
dev_err(dev, "get vpsl resource failed\n");
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
hw_dev->vpsl_base_addr = devm_ioremap_resource(dev, res);
|
||||
if (PTR_ERR(hw_dev->vpsl_base_addr) == -EBUSY) {
|
||||
resource_size_t offset = res->start;
|
||||
resource_size_t size = resource_size(res);
|
||||
|
||||
hw_dev->vpsl_base_addr = devm_ioremap(dev, offset, size);
|
||||
}
|
||||
|
||||
if (IS_ERR(hw_dev->vpsl_base_addr)) {
|
||||
dev_err(dev, "ioremap vpsl failed\n");
|
||||
ret = PTR_ERR(hw_dev->vpsl_base_addr);
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
memset(&hw_dev->max_in, 0, sizeof(hw_dev->max_in));
|
||||
if (!of_property_read_u32_array(node, "max-input", &hw_dev->max_in.w, 3)) {
|
||||
hw_dev->max_in.is_fix = true;
|
||||
@@ -1361,6 +1429,7 @@ static int rkisp_hw_probe(struct platform_device *pdev)
|
||||
mutex_init(&hw_dev->dev_lock);
|
||||
spin_lock_init(&hw_dev->rdbk_lock);
|
||||
atomic_set(&hw_dev->refcnt, 0);
|
||||
spin_lock_init(&hw_dev->reg_lock);
|
||||
spin_lock_init(&hw_dev->buf_lock);
|
||||
INIT_LIST_HEAD(&hw_dev->list);
|
||||
INIT_LIST_HEAD(&hw_dev->rpt_list);
|
||||
@@ -1518,6 +1587,16 @@ static int __maybe_unused rkisp_runtime_resume(struct device *dev)
|
||||
base = hw_dev->base_next_addr;
|
||||
memcpy_fromio(buf, base, RKISP_ISP_SW_REG_SIZE);
|
||||
}
|
||||
if (isp->sw_vpsl_base_addr && hw_dev->vpsl_base_addr) {
|
||||
u32 *flag;
|
||||
|
||||
buf = isp->sw_vpsl_base_addr;
|
||||
memset(buf, 0, VPSL_SW_MAX_SIZE * mult);
|
||||
flag = buf + VPSL_SW_REG_SIZE + VPSL_PYR_CTRL;
|
||||
*flag = SW_REG_CACHE;
|
||||
flag = buf + VPSL_PYR_CHN + VPSL_PYR_CTRL;
|
||||
*flag = SW_REG_CACHE;
|
||||
}
|
||||
default_sw_reg_flag(hw_dev->isp[i]);
|
||||
}
|
||||
rkisp_hw_enum_isp_size(hw_dev);
|
||||
|
||||
@@ -55,6 +55,7 @@ struct rkisp_hw_dev {
|
||||
void *sw_reg;
|
||||
void __iomem *base_addr;
|
||||
void __iomem *base_next_addr;
|
||||
void __iomem *vpsl_base_addr;
|
||||
struct clk *clks[RKISP_MAX_BUS_CLK];
|
||||
int num_clks;
|
||||
const struct isp_clk_info *clk_rate_tbl;
|
||||
@@ -77,7 +78,8 @@ struct rkisp_hw_dev {
|
||||
atomic_t refcnt;
|
||||
|
||||
struct rkisp_sram sram;
|
||||
|
||||
/* lock for reg */
|
||||
spinlock_t reg_lock;
|
||||
/* share buf for multi dev */
|
||||
spinlock_t buf_lock;
|
||||
struct rkisp_bridge_buf bufs[BRIDGE_BUF_MAX];
|
||||
|
||||
@@ -506,7 +506,9 @@ void rkisp_params_first_cfg(struct rkisp_isp_params_vdev *params_vdev,
|
||||
enum v4l2_quantization quantization)
|
||||
{
|
||||
struct rkisp_device *dev = params_vdev->dev;
|
||||
u32 val = rkisp_read(dev, ISP_HDRMGE_CTRL, false);
|
||||
|
||||
params_vdev->is_hdr = !!(val & SW_HDRMGE_EN);
|
||||
if (!params_vdev->is_first_cfg)
|
||||
return;
|
||||
params_vdev->is_first_cfg = false;
|
||||
|
||||
@@ -58,6 +58,7 @@ struct rkisp_isp_params_ops {
|
||||
void (*aiisp_event)(struct rkisp_isp_params_vdev *params_vdev, u32 irq);
|
||||
int (*aiisp_start)(struct rkisp_isp_params_vdev *params_vdev, struct rkisp_aiisp_st *st);
|
||||
int (*get_aiawb_buffd)(struct rkisp_isp_params_vdev *params_vdev, void *arg);
|
||||
void (*vpsl_update_regs)(struct rkisp_isp_params_vdev *params_vdev);
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -111,6 +112,7 @@ struct rkisp_isp_params_vdev {
|
||||
|
||||
bool is_subs_evt;
|
||||
bool is_first_cfg;
|
||||
bool is_hdr;
|
||||
};
|
||||
|
||||
static inline void
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -29,27 +29,80 @@ struct rkisp_isp_params_val_v35 {
|
||||
u32 buf_aiawb_cnt;
|
||||
int buf_aiawb_idx;
|
||||
|
||||
struct rkisp_dummy_buffer buf_3dnr_wgt;
|
||||
struct rkisp_dummy_buffer buf_3dnr_iir;
|
||||
struct rkisp_dummy_buffer buf_3dnr_ds;
|
||||
struct rkisp_dummy_buffer buf_gain;
|
||||
struct rkisp_dummy_buffer buf_bay3d_wgt[RKISP_BUFFER_MAX];
|
||||
struct rkisp_dummy_buffer buf_bay3d_iir[RKISP_BUFFER_MAX];
|
||||
struct rkisp_dummy_buffer buf_bay3d_ds[RKISP_BUFFER_MAX];
|
||||
struct rkisp_dummy_buffer buf_gain[RKISP_BUFFER_MAX];
|
||||
struct rkisp_dummy_buffer buf_aipre_gain[RKISP_BUFFER_MAX];
|
||||
struct rkisp_dummy_buffer buf_aiisp[RKISP_BUFFER_MAX];
|
||||
struct rkisp_dummy_buffer buf_vpsl[RKISP_BUFFER_MAX];
|
||||
|
||||
spinlock_t buf_lock;
|
||||
struct list_head iir_list;
|
||||
struct list_head gain_list;
|
||||
struct list_head aipre_gain_list;
|
||||
struct list_head vpsl_list;
|
||||
struct rkisp_dummy_buffer *pbuf_bay3d_iir;
|
||||
struct rkisp_dummy_buffer *pbuf_gain_wr;
|
||||
struct rkisp_dummy_buffer *pbuf_gain_rd;
|
||||
struct rkisp_dummy_buffer *pbuf_aipre_gain;
|
||||
struct rkisp_dummy_buffer *pbuf_vpsl;
|
||||
struct rkisp_dummy_buffer *pbuf_aiisp;
|
||||
|
||||
u32 bay3d_iir_rw_fmt;
|
||||
u32 bay3d_iir_offs;
|
||||
u32 bay3d_iir_stride;
|
||||
u32 bay3d_ds_size;
|
||||
u32 bay3d_iir_size;
|
||||
int bay3d_iir_cnt;
|
||||
int bay3d_iir_idx;
|
||||
int bay3d_iir_cur_idx;
|
||||
|
||||
u32 bay3d_ds_size;
|
||||
int bay3d_ds_cnt;
|
||||
int bay3d_ds_idx;
|
||||
int bay3d_ds_cur_idx;
|
||||
|
||||
u32 bay3d_wgt_size;
|
||||
int bay3d_wgt_cnt;
|
||||
int bay3d_wgt_idx;
|
||||
int bay3d_wgt_cur_idx;
|
||||
|
||||
int aiisp_cnt;
|
||||
int aiisp_cur_idx;
|
||||
|
||||
u32 gain_size;
|
||||
int gain_cnt;
|
||||
int gain_cur_idx;
|
||||
|
||||
u32 aipre_gain_stride;
|
||||
int aipre_gain_cnt;
|
||||
int aipre_gain_cur_idx;
|
||||
|
||||
int vpsl_cnt;
|
||||
int vpsl_cur_idx;
|
||||
|
||||
u32 vpsl_yraw_offs[VPSL_YRAW_CHN_MAX];
|
||||
u32 vpsl_yraw_stride[VPSL_YRAW_CHN_MAX];
|
||||
u32 vpsl_sig_offs[VPSL_SIG_CHN_MAX];
|
||||
u32 vpsl_sig_stride[VPSL_SIG_CHN_MAX];
|
||||
|
||||
u32 hist_blk_num;
|
||||
u32 enh_row;
|
||||
u32 enh_col;
|
||||
|
||||
bool yraw_sel;
|
||||
bool is_ae0_fe;
|
||||
bool is_ae3_fe;
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35)
|
||||
int rkisp_init_params_vdev_v35(struct rkisp_isp_params_vdev *params_vdev);
|
||||
void rkisp_uninit_params_vdev_v35(struct rkisp_isp_params_vdev *params_vdev);
|
||||
void rkisp_params_vpsl_mi_isr_v35(struct rkisp_isp_params_vdev *params_vdev, u32 mis_val);
|
||||
#else
|
||||
static inline int rkisp_init_params_vdev_v35(struct rkisp_isp_params_vdev *params_vdev) { return -EINVAL; }
|
||||
static inline void rkisp_uninit_params_vdev_v35(struct rkisp_isp_params_vdev *params_vdev) {}
|
||||
static inline void rkisp_params_vpsl_mi_isr_v35(struct rkisp_isp_params_vdev *params_vdev, u32 mis_val) {}
|
||||
#endif
|
||||
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35_DBG)
|
||||
int rkisp_get_params_v35(struct rkisp_isp_params_vdev *params_vdev, void *arg);
|
||||
|
||||
@@ -63,6 +63,7 @@ static int
|
||||
rkisp_stats_get_bay3d_stats(struct rkisp_isp_stats_vdev *stats_vdev,
|
||||
struct rkisp35_stat_buffer *pbuf)
|
||||
{
|
||||
struct rkisp_isp_params_val_v35 *priv = stats_vdev->dev->params_vdev.priv_val;
|
||||
struct isp33_bay3d_stat *bay3d;
|
||||
u32 i, val;
|
||||
|
||||
@@ -79,6 +80,12 @@ rkisp_stats_get_bay3d_stats(struct rkisp_isp_stats_vdev *stats_vdev,
|
||||
bay3d->sigma_y[i * 2 + 1] = (val >> 16) & 0xfff;
|
||||
}
|
||||
pbuf->meas_type |= ISP35_STAT_BAY3D;
|
||||
pbuf->stat.buf_bay3d_iir_index = priv->bay3d_iir_cur_idx;
|
||||
pbuf->stat.buf_bay3d_ds_index = priv->bay3d_ds_cur_idx;
|
||||
pbuf->stat.buf_bay3d_wgt_index = priv->bay3d_wgt_cur_idx;
|
||||
pbuf->stat.buf_gain_index = priv->gain_cur_idx;
|
||||
pbuf->stat.buf_aipre_gain_index = priv->aipre_gain_cur_idx;
|
||||
pbuf->stat.buf_vpsl_index = priv->vpsl_cur_idx;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@@ -191,14 +198,16 @@ rkisp_stats_update_buf(struct rkisp_isp_stats_vdev *stats_vdev)
|
||||
u32 val, addr = 0, offset = 0;
|
||||
int i, ret = 0;
|
||||
|
||||
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
|
||||
if (!stats_vdev->nxt_buf && !list_empty(&stats_vdev->stat)) {
|
||||
buf = list_first_entry(&stats_vdev->stat,
|
||||
struct rkisp_buffer, queue);
|
||||
list_del(&buf->queue);
|
||||
stats_vdev->nxt_buf = buf;
|
||||
if (!dev->is_aiisp_en || dev->is_aiisp_sync) {
|
||||
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
|
||||
if (!stats_vdev->nxt_buf && !list_empty(&stats_vdev->stat)) {
|
||||
buf = list_first_entry(&stats_vdev->stat,
|
||||
struct rkisp_buffer, queue);
|
||||
list_del(&buf->queue);
|
||||
stats_vdev->nxt_buf = buf;
|
||||
}
|
||||
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
|
||||
}
|
||||
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
|
||||
|
||||
if (stats_vdev->nxt_buf) {
|
||||
addr = stats_vdev->nxt_buf->buff_addr[0];
|
||||
@@ -376,29 +385,191 @@ rkisp_stats_info2ddr(struct rkisp_isp_stats_vdev *stats_vdev,
|
||||
}
|
||||
|
||||
static void
|
||||
rkisp_stats_send_meas_v35(struct rkisp_isp_stats_vdev *stats_vdev,
|
||||
struct rkisp_isp_readout_work *meas_work)
|
||||
rkisp_stats_send_meas_fe(struct rkisp_isp_stats_vdev *stats_vdev)
|
||||
{
|
||||
struct rkisp_isp_params_vdev *params_vdev = &stats_vdev->dev->params_vdev;
|
||||
struct rkisp_isp_params_val_v35 *priv = params_vdev->priv_val;
|
||||
struct rkisp_device *dev = stats_vdev->dev;
|
||||
struct rkisp35_stat_buffer *stat_tmp_buf, *stat_buf = NULL;
|
||||
struct rkisp_buffer *cur_buf = NULL;
|
||||
unsigned long flags = 0;
|
||||
u32 cur_frame_id, size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
|
||||
u32 val, ris = isp3_stats_read(stats_vdev, ISP3X_ISP_3A_RIS);
|
||||
u32 mask = ISP3X_3A_RAWAF;
|
||||
u64 ns;
|
||||
|
||||
if (!dev->is_aiisp_en || dev->is_aiisp_sync)
|
||||
return;
|
||||
if (priv->is_ae0_fe)
|
||||
mask |= ISP3X_3A_RAWAE_CH0 | ISP3X_3A_RAWHIST_CH0;
|
||||
if (priv->is_ae3_fe)
|
||||
mask |= ISP3X_3A_RAWAE_BIG | ISP3X_3A_RAWHIST_BIG;
|
||||
if (ris & mask) {
|
||||
isp3_stats_write(stats_vdev, ISP3X_ISP_3A_ICR, ris & mask);
|
||||
val = isp3_stats_read(stats_vdev, ISP3X_RAWAF_CTRL);
|
||||
if (val & ISP35_3A_MEAS_DONE)
|
||||
isp3_module_done(stats_vdev, ISP3X_RAWAF_CTRL, val);
|
||||
if (ris & ISP3X_3A_RAWAE_CH0) {
|
||||
val = isp3_stats_read(stats_vdev, ISP3X_RAWAE_LITE_BASE);
|
||||
if (val & ISP35_3A_MEAS_DONE)
|
||||
isp3_module_done(stats_vdev, ISP3X_RAWAE_LITE_BASE, val);
|
||||
}
|
||||
if (ris & ISP3X_3A_RAWHIST_CH0) {
|
||||
val = isp3_stats_read(stats_vdev, ISP3X_RAWHIST_LITE_BASE);
|
||||
if (val & ISP35_3A_MEAS_DONE)
|
||||
isp3_module_done(stats_vdev, ISP3X_RAWHIST_LITE_BASE, val);
|
||||
}
|
||||
if (ris & ISP3X_3A_RAWAE_BIG) {
|
||||
val = isp3_stats_read(stats_vdev, ISP3X_RAWAE_BIG1_BASE);
|
||||
if (val & ISP35_3A_MEAS_DONE)
|
||||
isp3_module_done(stats_vdev, ISP3X_RAWAE_BIG1_BASE, val);
|
||||
}
|
||||
if (ris & ISP3X_3A_RAWHIST_BIG) {
|
||||
val = isp3_stats_read(stats_vdev, ISP3X_RAWHIST_BIG1_BASE);
|
||||
if (val & ISP35_3A_MEAS_DONE)
|
||||
isp3_module_done(stats_vdev, ISP3X_RAWHIST_BIG1_BASE, val);
|
||||
}
|
||||
}
|
||||
rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, &ns, true);
|
||||
if (!ns)
|
||||
ns = ktime_get_ns();
|
||||
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
|
||||
if (!list_empty(&stats_vdev->stat)) {
|
||||
cur_buf = list_first_entry(&stats_vdev->stat,
|
||||
struct rkisp_buffer, queue);
|
||||
list_del(&cur_buf->queue);
|
||||
}
|
||||
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
|
||||
|
||||
if (cur_buf) {
|
||||
stat_buf = cur_buf->vaddr[0];
|
||||
stat_tmp_buf = stats_vdev->stats_buf[0].vaddr;
|
||||
rkisp_finish_buffer(dev, &stats_vdev->stats_buf[0]);
|
||||
|
||||
stat_buf->frame_id = cur_frame_id;
|
||||
stat_buf->params_id = params_vdev->cur_fe_frame_id;
|
||||
stat_buf->stat.info2ddr.buf_fd = -1;
|
||||
stat_buf->stat.info2ddr.owner = 0;
|
||||
stat_buf->stat.buf_aiawb_index = -1;
|
||||
stat_buf->stat.buf_bay3d_iir_index = -1;
|
||||
stat_buf->stat.buf_bay3d_ds_index = -1;
|
||||
stat_buf->stat.buf_bay3d_wgt_index = -1;
|
||||
stat_buf->stat.buf_aipre_gain_index = -1;
|
||||
stat_buf->stat.buf_gain_index = -1;
|
||||
stat_buf->stat.buf_vpsl_index = -1;
|
||||
}
|
||||
if (ris & ISP3X_3A_RAWAE_CH0 && stat_buf && stat_tmp_buf) {
|
||||
memcpy(&stat_buf->stat.rawae0,
|
||||
&stat_tmp_buf->stat.rawae0, sizeof(struct isp33_rawae_stat));
|
||||
stat_buf->meas_type |= ISP35_STAT_RAWAE0;
|
||||
}
|
||||
if (ris & ISP3X_3A_RAWHIST_CH0 && stat_buf && stat_tmp_buf) {
|
||||
memcpy(&stat_buf->stat.rawhist0,
|
||||
&stat_tmp_buf->stat.rawhist0, sizeof(struct isp33_rawhist_stat));
|
||||
stat_buf->meas_type |= ISP35_STAT_RAWHST0;
|
||||
}
|
||||
if (ris & ISP3X_3A_RAWAE_BIG && stat_buf && stat_tmp_buf) {
|
||||
memcpy(&stat_buf->stat.rawae3,
|
||||
&stat_tmp_buf->stat.rawae3, sizeof(struct isp33_rawae_stat));
|
||||
stat_buf->meas_type |= ISP35_STAT_RAWAE3;
|
||||
}
|
||||
if (ris & ISP3X_3A_RAWHIST_BIG && stat_buf && stat_tmp_buf) {
|
||||
memcpy(&stat_buf->stat.rawhist3,
|
||||
&stat_tmp_buf->stat.rawhist3, sizeof(struct isp33_rawhist_stat));
|
||||
stat_buf->meas_type |= ISP35_STAT_RAWHST3;
|
||||
}
|
||||
if (ris & ISP3X_3A_RAWAF && stat_buf && stat_tmp_buf) {
|
||||
memcpy(&stat_buf->stat.rawaf,
|
||||
&stat_tmp_buf->stat.rawaf, sizeof(struct isp39_rawaf_stat));
|
||||
stat_buf->meas_type |= ISP35_STAT_RAWAF;
|
||||
}
|
||||
if (stat_buf)
|
||||
rkisp_stats_get_bay3d_stats(stats_vdev, stat_buf);
|
||||
if (cur_buf) {
|
||||
cur_buf->vb.sequence = cur_frame_id;
|
||||
cur_buf->vb.vb2_buf.timestamp = ns;
|
||||
vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, size);
|
||||
vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
|
||||
}
|
||||
v4l2_dbg(4, rkisp_debug, &stats_vdev->dev->v4l2_dev,
|
||||
"%s seq:%d params_id:%d ris:0x%x buf:%p meas_type:0x%x\n",
|
||||
__func__,
|
||||
cur_frame_id, params_vdev->cur_fe_frame_id, ris,
|
||||
cur_buf, !stat_buf ? 0 : stat_buf->meas_type);
|
||||
}
|
||||
|
||||
static void
|
||||
rkisp_stats_send_meas(struct rkisp_isp_stats_vdev *stats_vdev)
|
||||
{
|
||||
struct rkisp_isp_params_vdev *params_vdev = &stats_vdev->dev->params_vdev;
|
||||
struct rkisp_isp_params_val_v35 *priv = params_vdev->priv_val;
|
||||
struct rkisp_device *dev = stats_vdev->dev;
|
||||
struct rkisp_buffer *cur_buf = stats_vdev->cur_buf;
|
||||
struct rkisp35_stat_buffer *cur_stat_buf = NULL;
|
||||
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
|
||||
u32 cur_frame_id = meas_work->frame_id;
|
||||
struct rkisp35_stat_buffer *stat_tmp_buf = NULL, *cur_stat_buf = NULL;
|
||||
u32 cur_frame_id, size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
|
||||
u32 val, mask, ris = isp3_stats_read(stats_vdev, ISP3X_ISP_3A_RIS);
|
||||
u64 ns;
|
||||
bool is_dummy = false;
|
||||
unsigned long flags = 0;
|
||||
|
||||
mask = ISP3X_3A_RAWAWB | ISP35_AIAWB_DONE | ISP3X_3A_DDR_DONE;
|
||||
if (!dev->is_aiisp_en || dev->is_aiisp_sync) {
|
||||
mask |= ISP3X_3A_RAWAF | ISP3X_3A_RAWAE_CH0 | ISP3X_3A_RAWHIST_CH0 |
|
||||
ISP3X_3A_RAWAE_BIG | ISP3X_3A_RAWHIST_BIG;
|
||||
}
|
||||
if (dev->is_aiisp_en && !priv->is_ae0_fe)
|
||||
mask |= ISP3X_3A_RAWHIST_CH0 | ISP3X_3A_RAWAE_CH0;
|
||||
if (dev->is_aiisp_en && !priv->is_ae3_fe)
|
||||
mask |= ISP3X_3A_RAWAE_BIG | ISP3X_3A_RAWHIST_BIG;
|
||||
if (ris & mask) {
|
||||
isp3_stats_write(stats_vdev, ISP3X_ISP_3A_ICR, ris & mask);
|
||||
if (dev->is_aiisp_en && !dev->is_aiisp_sync) {
|
||||
val = isp3_stats_read(stats_vdev, ISP3X_RAWAWB_CTRL);
|
||||
if (val & ISP35_3A_MEAS_DONE)
|
||||
isp3_module_done(stats_vdev, ISP3X_RAWAWB_CTRL, val);
|
||||
if (ris & ISP3X_3A_RAWAE_CH0) {
|
||||
val = isp3_stats_read(stats_vdev, ISP3X_RAWAE_LITE_BASE);
|
||||
if (val & ISP35_3A_MEAS_DONE)
|
||||
isp3_module_done(stats_vdev, ISP3X_RAWAE_LITE_BASE, val);
|
||||
}
|
||||
if (ris & ISP3X_3A_RAWHIST_CH0) {
|
||||
val = isp3_stats_read(stats_vdev, ISP3X_RAWHIST_LITE_BASE);
|
||||
if (val & ISP35_3A_MEAS_DONE)
|
||||
isp3_module_done(stats_vdev, ISP3X_RAWHIST_LITE_BASE, val);
|
||||
}
|
||||
if (ris & ISP3X_3A_RAWAE_BIG) {
|
||||
val = isp3_stats_read(stats_vdev, ISP3X_RAWAE_BIG1_BASE);
|
||||
if (val & ISP35_3A_MEAS_DONE)
|
||||
isp3_module_done(stats_vdev, ISP3X_RAWAE_BIG1_BASE, val);
|
||||
}
|
||||
if (ris & ISP3X_3A_RAWHIST_BIG) {
|
||||
val = isp3_stats_read(stats_vdev, ISP3X_RAWHIST_BIG1_BASE);
|
||||
if (val & ISP35_3A_MEAS_DONE)
|
||||
isp3_module_done(stats_vdev, ISP3X_RAWHIST_BIG1_BASE, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, &ns, !dev->is_aiisp_en);
|
||||
if (!ns)
|
||||
ns = ktime_get_ns();
|
||||
if (dev->is_aiisp_en && !dev->is_aiisp_sync) {
|
||||
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
|
||||
if (!list_empty(&stats_vdev->stat)) {
|
||||
cur_buf = list_first_entry(&stats_vdev->stat,
|
||||
struct rkisp_buffer, queue);
|
||||
list_del(&cur_buf->queue);
|
||||
}
|
||||
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
|
||||
stat_tmp_buf = stats_vdev->stats_buf[0].vaddr;
|
||||
rkisp_finish_buffer(dev, &stats_vdev->stats_buf[0]);
|
||||
}
|
||||
if (!stats_vdev->rdbk_drop) {
|
||||
if (!cur_buf && stats_vdev->stats_buf[0].mem_priv) {
|
||||
rkisp_finish_buffer(stats_vdev->dev, &stats_vdev->stats_buf[0]);
|
||||
cur_stat_buf = stats_vdev->stats_buf[0].vaddr;
|
||||
cur_stat_buf->frame_id = cur_frame_id;
|
||||
cur_stat_buf->params_id = params_vdev->cur_frame_id;
|
||||
is_dummy = true;
|
||||
} else if (cur_buf) {
|
||||
cur_stat_buf = cur_buf->vaddr[0];
|
||||
cur_stat_buf->frame_id = cur_frame_id;
|
||||
cur_stat_buf->params_id = params_vdev->cur_frame_id;
|
||||
}
|
||||
|
||||
/* buffer done when frame of right handle */
|
||||
@@ -408,8 +579,6 @@ rkisp_stats_send_meas_v35(struct rkisp_isp_stats_vdev *stats_vdev,
|
||||
is_dummy = false;
|
||||
} else if (cur_stat_buf) {
|
||||
cur_stat_buf = (void *)cur_stat_buf + size / 2;
|
||||
cur_stat_buf->frame_id = cur_frame_id;
|
||||
cur_stat_buf->params_id = params_vdev->cur_frame_id;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -420,47 +589,69 @@ rkisp_stats_send_meas_v35(struct rkisp_isp_stats_vdev *stats_vdev,
|
||||
stats_vdev->cur_buf = stats_vdev->nxt_buf;
|
||||
stats_vdev->nxt_buf = NULL;
|
||||
}
|
||||
rkisp_stats_update_buf(stats_vdev);
|
||||
if (!dev->is_aiisp_en || dev->is_aiisp_sync)
|
||||
rkisp_stats_update_buf(stats_vdev);
|
||||
}
|
||||
} else {
|
||||
cur_buf = NULL;
|
||||
}
|
||||
|
||||
if (cur_stat_buf) {
|
||||
cur_stat_buf->stat.buf_aiawb_index = -1;
|
||||
cur_stat_buf->frame_id = cur_frame_id;
|
||||
cur_stat_buf->params_id = params_vdev->cur_frame_id;
|
||||
cur_stat_buf->stat.info2ddr.buf_fd = -1;
|
||||
cur_stat_buf->stat.info2ddr.owner = 0;
|
||||
cur_stat_buf->stat.buf_aiawb_index = -1;
|
||||
cur_stat_buf->stat.buf_bay3d_iir_index = -1;
|
||||
cur_stat_buf->stat.buf_bay3d_ds_index = -1;
|
||||
cur_stat_buf->stat.buf_bay3d_wgt_index = -1;
|
||||
cur_stat_buf->stat.buf_aipre_gain_index = -1;
|
||||
cur_stat_buf->stat.buf_gain_index = -1;
|
||||
cur_stat_buf->stat.buf_vpsl_index = -1;
|
||||
}
|
||||
|
||||
if (meas_work->isp3a_ris & ISP3X_3A_RAWAWB && cur_stat_buf)
|
||||
cur_stat_buf->meas_type |= ISP35_STAT_RAWAWB;
|
||||
|
||||
if (meas_work->isp3a_ris & ISP3X_3A_RAWAF && cur_stat_buf)
|
||||
if (ris & (mask & ISP3X_3A_RAWAF) && cur_stat_buf)
|
||||
cur_stat_buf->meas_type |= ISP35_STAT_RAWAF;
|
||||
|
||||
if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_BIG && cur_stat_buf)
|
||||
cur_stat_buf->meas_type |= ISP35_STAT_RAWAE3;
|
||||
|
||||
if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_BIG && cur_stat_buf)
|
||||
cur_stat_buf->meas_type |= ISP35_STAT_RAWHST3;
|
||||
|
||||
if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH0 && cur_stat_buf)
|
||||
if (ris & (mask & ISP3X_3A_RAWAE_CH0) && cur_stat_buf) {
|
||||
cur_stat_buf->meas_type |= ISP35_STAT_RAWAE0;
|
||||
|
||||
if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH0 && cur_stat_buf)
|
||||
if (dev->is_aiisp_en && !dev->is_aiisp_sync && stat_tmp_buf)
|
||||
memcpy(&cur_stat_buf->stat.rawae0,
|
||||
&stat_tmp_buf->stat.rawae0, sizeof(struct isp33_rawae_stat));
|
||||
}
|
||||
if (ris & (mask & ISP3X_3A_RAWHIST_CH0) && cur_stat_buf) {
|
||||
cur_stat_buf->meas_type |= ISP35_STAT_RAWHST0;
|
||||
|
||||
if (meas_work->isp3a_ris & ISP35_AIAWB_DONE && cur_stat_buf)
|
||||
if (dev->is_aiisp_en && !dev->is_aiisp_sync && stat_tmp_buf)
|
||||
memcpy(&cur_stat_buf->stat.rawhist0,
|
||||
&stat_tmp_buf->stat.rawhist0, sizeof(struct isp33_rawhist_stat));
|
||||
}
|
||||
if (ris & (mask & ISP3X_3A_RAWAE_BIG) && cur_stat_buf) {
|
||||
cur_stat_buf->meas_type |= ISP35_STAT_RAWAE3;
|
||||
if (dev->is_aiisp_en && !dev->is_aiisp_sync && stat_tmp_buf)
|
||||
memcpy(&cur_stat_buf->stat.rawae3,
|
||||
&stat_tmp_buf->stat.rawae3, sizeof(struct isp33_rawae_stat));
|
||||
}
|
||||
if (ris & (mask & ISP3X_3A_RAWHIST_BIG) && cur_stat_buf) {
|
||||
cur_stat_buf->meas_type |= ISP35_STAT_RAWHST3;
|
||||
if (dev->is_aiisp_en && !dev->is_aiisp_sync && stat_tmp_buf)
|
||||
memcpy(&cur_stat_buf->stat.rawhist3,
|
||||
&stat_tmp_buf->stat.rawhist3, sizeof(struct isp33_rawhist_stat));
|
||||
}
|
||||
if (ris & (mask & ISP3X_3A_RAWAWB) && cur_stat_buf) {
|
||||
cur_stat_buf->meas_type |= ISP35_STAT_RAWAWB;
|
||||
if (dev->is_aiisp_en && !dev->is_aiisp_sync && stat_tmp_buf)
|
||||
memcpy(&cur_stat_buf->stat.rawawb,
|
||||
&stat_tmp_buf->stat.rawawb, sizeof(struct isp33_rawawb_stat));
|
||||
}
|
||||
if (ris & ISP35_AIAWB_DONE && cur_stat_buf)
|
||||
rkisp_stats_get_aiawb_stats(stats_vdev, cur_stat_buf);
|
||||
if (meas_work->isp3a_ris & ISP35_AWBSYNC_DONE && cur_stat_buf)
|
||||
if (ris & ISP35_AWBSYNC_DONE && cur_stat_buf)
|
||||
rkisp_stats_get_awbsync_stats(stats_vdev, cur_stat_buf);
|
||||
|
||||
if (meas_work->isp_ris & ISP3X_FRAME) {
|
||||
if (!dev->is_aiisp_en || dev->is_aiisp_sync)
|
||||
rkisp_stats_get_bay3d_stats(stats_vdev, cur_stat_buf);
|
||||
rkisp_stats_get_sharp_stats(stats_vdev, cur_stat_buf);
|
||||
rkisp_stats_get_enh_stats(stats_vdev, cur_stat_buf);
|
||||
rkisp_stats_get_hist_stats(stats_vdev, cur_stat_buf);
|
||||
}
|
||||
rkisp_stats_get_sharp_stats(stats_vdev, cur_stat_buf);
|
||||
rkisp_stats_get_enh_stats(stats_vdev, cur_stat_buf);
|
||||
rkisp_stats_get_hist_stats(stats_vdev, cur_stat_buf);
|
||||
|
||||
if (cur_stat_buf && (dev->is_first_double || dev->is_wait_aiq)) {
|
||||
cur_stat_buf->meas_type |= ISP35_STAT_RTT_FST;
|
||||
@@ -481,20 +672,16 @@ rkisp_stats_send_meas_v35(struct rkisp_isp_stats_vdev *stats_vdev,
|
||||
}
|
||||
}
|
||||
if (cur_buf && cur_stat_buf) {
|
||||
cur_stat_buf->frame_id = cur_frame_id;
|
||||
cur_stat_buf->params_id = params_vdev->cur_frame_id;
|
||||
cur_stat_buf->stat.info2ddr.buf_fd = -1;
|
||||
cur_stat_buf->stat.info2ddr.owner = 0;
|
||||
rkisp_stats_info2ddr(stats_vdev, cur_stat_buf);
|
||||
|
||||
vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, size);
|
||||
cur_buf->vb.sequence = cur_frame_id;
|
||||
cur_buf->vb.vb2_buf.timestamp = meas_work->timestamp;
|
||||
cur_buf->vb.vb2_buf.timestamp = ns;
|
||||
vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
|
||||
}
|
||||
v4l2_dbg(4, rkisp_debug, &stats_vdev->dev->v4l2_dev,
|
||||
"%s seq:%d params_id:%d ris:0x%x buf:%p meas_type:0x%x aiawb(fd:%d 0x%x)\n",
|
||||
__func__, cur_frame_id, params_vdev->cur_frame_id, meas_work->isp3a_ris,
|
||||
"%s seq:%d params_id:%d ris:0x%x buf:%p meas_type:0x%x aiawb(idx:%d 0x%x)\n",
|
||||
__func__, cur_frame_id, params_vdev->cur_frame_id, ris,
|
||||
cur_buf, !cur_stat_buf ? 0 : cur_stat_buf->meas_type,
|
||||
!cur_stat_buf ? -1 : cur_stat_buf->stat.buf_aiawb_index,
|
||||
isp3_stats_read(stats_vdev, ISP35_AIAWB_WR_BASE_SHD));
|
||||
@@ -504,27 +691,12 @@ static void
|
||||
rkisp_stats_isr_v35(struct rkisp_isp_stats_vdev *stats_vdev,
|
||||
u32 isp_ris, u32 isp3a_ris)
|
||||
{
|
||||
struct rkisp_isp_readout_work work;
|
||||
u32 cur_frame_id, isp_mis_tmp = 0;
|
||||
u32 temp_isp3a_ris;
|
||||
|
||||
rkisp_dmarx_get_frame(stats_vdev->dev, &cur_frame_id, NULL, NULL, true);
|
||||
|
||||
temp_isp3a_ris = isp3_stats_read(stats_vdev, ISP3X_ISP_3A_RIS);
|
||||
isp_mis_tmp = temp_isp3a_ris;
|
||||
if (isp_mis_tmp)
|
||||
isp3_stats_write(stats_vdev, ISP3X_ISP_3A_ICR, isp_mis_tmp);
|
||||
|
||||
rkisp_pdaf_isr(stats_vdev->dev);
|
||||
|
||||
if (isp_ris & ISP3X_FRAME) {
|
||||
work.readout = RKISP_ISP_READOUT_MEAS;
|
||||
work.frame_id = cur_frame_id;
|
||||
work.isp_ris = isp_ris;
|
||||
work.isp3a_ris = temp_isp3a_ris;
|
||||
work.timestamp = ktime_get_ns();
|
||||
rkisp_stats_send_meas_v35(stats_vdev, &work);
|
||||
}
|
||||
if (isp_ris & ISP3X_BAY3D_FRM_END)
|
||||
rkisp_stats_send_meas_fe(stats_vdev);
|
||||
if (isp_ris & ISP3X_FRAME)
|
||||
rkisp_stats_send_meas(stats_vdev);
|
||||
}
|
||||
|
||||
static void
|
||||
@@ -583,7 +755,9 @@ rkisp_stats_first_ddr_config_v35(struct rkisp_isp_stats_vdev *stats_vdev)
|
||||
if (dev->hw_dev->is_single)
|
||||
rkisp_unite_set_bits(dev, ISP3X_SWS_CFG, 0, ISP3X_3A_DDR_WRITE_EN, false);
|
||||
val = rkisp_read(dev, ISP39_W3A_CTRL0, false);
|
||||
val |= ISP39_W3A_EN | ISP39_W3A_AUTO_CLR_EN | ISP39_W3A_FORCE_UPD;
|
||||
val |= ISP39_W3A_EN | ISP39_W3A_FORCE_UPD;
|
||||
if (!dev->is_aiisp_en || dev->is_aiisp_sync)
|
||||
val |= ISP39_W3A_AUTO_CLR_EN;
|
||||
if (pdaf_vdev && pdaf_vdev->streaming) {
|
||||
val |= ISP39_W3A_PDAF_EN;
|
||||
rkisp_pdaf_update_buf(dev);
|
||||
@@ -611,7 +785,8 @@ rkisp_stats_next_ddr_config_v35(struct rkisp_isp_stats_vdev *stats_vdev)
|
||||
return;
|
||||
/* pingpong buf */
|
||||
if (hw->is_single) {
|
||||
rkisp_stats_update_buf(stats_vdev);
|
||||
if (!dev->is_aiisp_en || dev->is_aiisp_sync)
|
||||
rkisp_stats_update_buf(stats_vdev);
|
||||
if (pdaf_vdev && pdaf_vdev->streaming)
|
||||
rkisp_pdaf_update_buf(dev);
|
||||
}
|
||||
|
||||
@@ -1195,7 +1195,17 @@ static void isp35_show(struct rkisp_device *dev, struct seq_file *p)
|
||||
rkisp_read(dev, ISP35_B3DLDC_ADR_STS, false),
|
||||
rkisp_read(dev, ISP35_B3DLDC_CTRL, false),
|
||||
!(val & BIT(8)), !!(tmp & BIT(20)), !!(tmp & BIT(21)), !!(tmp & BIT(22)),
|
||||
priv->buf_3dnr_iir.size, priv->buf_3dnr_ds.size, priv->buf_3dnr_wgt.size);
|
||||
priv->buf_bay3d_iir[0].size, priv->buf_bay3d_ds[0].size, priv->buf_bay3d_wgt[0].size);
|
||||
val = rkisp_read(dev, ISP35_AI_CTRL, false);
|
||||
seq_printf(p, "%-10s %s(0x%x) vpsl(ctrl:0x%x chn:0x%x), aiisp(idx:%d cnt:%d)\n"
|
||||
"\t iir(idx:%d cnt:%d) gain(idx:%d cnt:%d) aipre(idx:%d cnt:%d) vpsl(idx:%d cnt:%d)\n",
|
||||
"AINR", (val & 1) ? "ON" : "OFF", val,
|
||||
vpsl_read(dev, VPSL_PYR_CTRL, false), vpsl_read(dev, VPSL_PYR_CHN, false),
|
||||
priv->aiisp_cur_idx, priv->aiisp_cnt,
|
||||
priv->bay3d_iir_cur_idx, priv->bay3d_iir_cnt,
|
||||
priv->gain_cur_idx, priv->gain_cnt,
|
||||
priv->aipre_gain_cur_idx, priv->aipre_gain_cnt,
|
||||
priv->vpsl_cur_idx, priv->vpsl_cnt);
|
||||
val = rkisp_read(dev, ISP3X_YNR_GLOBAL_CTRL, false);
|
||||
seq_printf(p, "%-10s %s(0x%x) bypass(hi:%d mi:%d lo:%d) lp_en:%d\n", "YNR",
|
||||
(val & 1) ? "ON" : "OFF", val,
|
||||
|
||||
@@ -37,6 +37,7 @@
|
||||
#include "dev.h"
|
||||
#include "regs_v2x.h"
|
||||
#include "regs_v3x.h"
|
||||
#include "vpsl_reg.h"
|
||||
|
||||
#define CIF_ISP_PACK_4BYTE(a, b, c, d) \
|
||||
(((a) & 0xFF) << 0 | ((b) & 0xFF) << 8 | \
|
||||
|
||||
@@ -50,6 +50,7 @@
|
||||
#include "isp_external.h"
|
||||
#include "regs.h"
|
||||
#include "rkisp_tb_helper.h"
|
||||
#include "isp_params_v35.h"
|
||||
|
||||
#define ISP_V4L2_EVENT_ELEMS 4
|
||||
|
||||
@@ -683,6 +684,7 @@ static void rkisp_update_list_reg(struct rkisp_device *dev)
|
||||
val |= ISP3X_3A_DDR_WRITE_EN;
|
||||
writel(val, hw->base_addr + ISP3X_SWS_CFG);
|
||||
}
|
||||
dev->params_vdev.ops->vpsl_update_regs(&dev->params_vdev);
|
||||
}
|
||||
if (dev->isp_ver >= ISP_V33) {
|
||||
val = rkisp_read(dev, ISP39_W3A_CTRL0, false);
|
||||
@@ -2430,8 +2432,8 @@ static int rkisp_isp_start(struct rkisp_device *dev)
|
||||
u32 val;
|
||||
|
||||
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
|
||||
"%s refcnt:%d link_num:%d\n", __func__,
|
||||
atomic_read(&hw->refcnt), hw->dev_link_num);
|
||||
"%s refcnt:%d link_num:%d unite_div:%d\n", __func__,
|
||||
atomic_read(&hw->refcnt), hw->dev_link_num, dev->unite_div);
|
||||
|
||||
dev->cap_dev.is_done_early = false;
|
||||
if (dev->cap_dev.wait_line >= dev->isp_sdev.out_crop.height)
|
||||
@@ -3862,7 +3864,7 @@ static void rkisp_config_aiisp(struct rkisp_device *dev)
|
||||
goto unlock;
|
||||
dev->is_aiisp_upd = false;
|
||||
if (dev->is_aiisp_en) {
|
||||
en = ISP39_AIISP_EN;
|
||||
en = (dev->isp_ver == ISP_V39) ? ISP39_AIISP_EN : ISP35_AIISP_EN;
|
||||
irq = ISP39_AIISP_LINECNT_DONE;
|
||||
if (dev->aiisp_cfg.rd_linecnt)
|
||||
irq |= ISP3X_OUT_FRM_QUARTER;
|
||||
@@ -3871,14 +3873,14 @@ static void rkisp_config_aiisp(struct rkisp_device *dev)
|
||||
en = 0;
|
||||
}
|
||||
irq_mask = ISP39_AIISP_LINECNT_DONE | ISP3X_OUT_FRM_QUARTER;
|
||||
en_mask = ISP39_AIISP_EN;
|
||||
en_mask = (dev->isp_ver == ISP_V39) ? ISP39_AIISP_EN : ISP35_AIISP_EN;
|
||||
|
||||
if (dev->aiisp_cfg.rd_linecnt >= h)
|
||||
rd_line = h - 1;
|
||||
else
|
||||
rd_line = dev->aiisp_cfg.rd_linecnt;
|
||||
if (dev->aiisp_cfg.wr_linecnt >= h)
|
||||
wr_line = (h - 1) << 16;
|
||||
if (dev->aiisp_cfg.wr_linecnt >= (h - 10))
|
||||
wr_line = (h - 10) << 16;
|
||||
else
|
||||
wr_line = dev->aiisp_cfg.wr_linecnt << 16;
|
||||
|
||||
@@ -3886,7 +3888,10 @@ static void rkisp_config_aiisp(struct rkisp_device *dev)
|
||||
rkisp_write(dev, ISP32_ISP_IRQ_CFG1, wr_line, false);
|
||||
rkisp_write(dev, ISP39_SLICE_ST_CTRL, 0, false);
|
||||
rkisp_set_bits(dev, CIF_ISP_IMSC, irq_mask, irq, false);
|
||||
rkisp_set_bits(dev, ISP3X_MI_RD_CTRL2, en_mask, en, false);
|
||||
if (dev->isp_ver == ISP_V39)
|
||||
rkisp_set_bits(dev, ISP3X_MI_RD_CTRL2, en_mask, en, false);
|
||||
else
|
||||
rkisp_set_bits(dev, ISP35_AI_CTRL, en_mask, en, false);
|
||||
unlock:
|
||||
spin_unlock_irqrestore(&dev->aiisp_lock, lock_flags);
|
||||
}
|
||||
@@ -3896,7 +3901,7 @@ static int rkisp_set_aiisp_linecnt(struct rkisp_device *dev,
|
||||
{
|
||||
unsigned long lock_flags = 0;
|
||||
|
||||
if (dev->isp_ver != ISP_V39)
|
||||
if (dev->isp_ver != ISP_V39 && dev->isp_ver != ISP_V35)
|
||||
return -EINVAL;
|
||||
spin_lock_irqsave(&dev->aiisp_lock, lock_flags);
|
||||
dev->is_aiisp_en = !!cfg->mode;
|
||||
@@ -3911,7 +3916,7 @@ static int rkisp_get_aiisp_linecnt(struct rkisp_device *dev,
|
||||
{
|
||||
unsigned long lock_flags = 0;
|
||||
|
||||
if (dev->isp_ver != ISP_V39)
|
||||
if (dev->isp_ver != ISP_V39 && dev->isp_ver != ISP_V35)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&dev->aiisp_lock, lock_flags);
|
||||
@@ -3982,7 +3987,10 @@ end:
|
||||
rkisp_sditf_sof(dev, 0);
|
||||
|
||||
rkisp_check_mi_ends_mask(dev);
|
||||
rkisp_set_bits(dev, ISP3X_MI_RD_CTRL2, 0, ISP39_AIISP_ST, true);
|
||||
if (dev->isp_ver == ISP_V39)
|
||||
rkisp_set_bits(dev, ISP3X_MI_RD_CTRL2, 0, ISP39_AIISP_ST, true);
|
||||
else
|
||||
rkisp_set_bits(dev, ISP35_AI_CTRL, 0, ISP35_AIISP_ST, true);
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
@@ -5022,7 +5030,7 @@ vs_skip:
|
||||
isp_mis_tmp);
|
||||
}
|
||||
|
||||
if (isp_mis & ISP39_AIISP_LINECNT_DONE && dev->isp_ver == ISP_V39) {
|
||||
if (isp_mis & ISP39_AIISP_LINECNT_DONE) {
|
||||
writel(ISP39_AIISP_LINECNT_DONE, base + CIF_ISP_ICR);
|
||||
rkisp_aiisp_irq_event(dev, ISP39_AIISP_LINECNT_DONE);
|
||||
}
|
||||
@@ -5210,6 +5218,12 @@ vs_skip:
|
||||
}
|
||||
}
|
||||
|
||||
void rkisp_vpsl_mi_isr(struct rkisp_device *dev, u32 mis_val)
|
||||
{
|
||||
if (dev->isp_ver == ISP_V35)
|
||||
rkisp_params_vpsl_mi_isr_v35(&dev->params_vdev, mis_val);
|
||||
}
|
||||
|
||||
irqreturn_t rkisp_vs_isr_handler(int irq, void *ctx)
|
||||
{
|
||||
struct device *dev = ctx;
|
||||
|
||||
@@ -198,6 +198,8 @@ void rkisp_rx_buf_pool_free(struct rkisp_device *dev);
|
||||
int rkisp_expander_config(struct rkisp_device *dev,
|
||||
struct rkmodule_hdr_cfg *cfg, bool on);
|
||||
|
||||
void rkisp_vpsl_mi_isr(struct rkisp_device *dev, u32 mis_val);
|
||||
|
||||
static inline
|
||||
struct ispsd_out_fmt *rkisp_get_ispsd_out_fmt(struct rkisp_isp_subdev *isp_sdev)
|
||||
{
|
||||
|
||||
252
drivers/media/platform/rockchip/isp/vpsl_reg.h
Normal file
252
drivers/media/platform/rockchip/isp/vpsl_reg.h
Normal file
@@ -0,0 +1,252 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*
|
||||
* Copyright (C) 2025 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _VPSL_REG_H
|
||||
#define _VPSL_REG_H
|
||||
#include "dev.h"
|
||||
|
||||
#define VPSL_BASE 0x00000000
|
||||
#define VPSL_CTRL (VPSL_BASE + 0x00000)
|
||||
#define VPSL_PYR_CTRL (VPSL_BASE + 0x00004)
|
||||
#define VPSL_PYR_CHN (VPSL_BASE + 0x00008)
|
||||
#define VPSL_VERSION (VPSL_BASE + 0x0000C)
|
||||
#define VPSL_UPDATE (VPSL_BASE + 0x00010)
|
||||
#define VPSL_CLK_EN (VPSL_BASE + 0x00014)
|
||||
#define VPSL_CLK_GATE (VPSL_BASE + 0x00018)
|
||||
#define VPSL_RESET (VPSL_BASE + 0x0001C)
|
||||
#define VPSL_PYR_SIGMA_LUT (VPSL_BASE + 0x00020)
|
||||
#define VPSL_IRQ_CFG (VPSL_BASE + 0x00050)
|
||||
#define VPSL_IMSC (VPSL_BASE + 0x00070)
|
||||
#define VPSL_RIS (VPSL_BASE + 0x00074)
|
||||
#define VPSL_MIS (VPSL_BASE + 0x00078)
|
||||
#define VPSL_ICR (VPSL_BASE + 0x0007C)
|
||||
#define VPSL_ISR (VPSL_BASE + 0x00080)
|
||||
#define VPSL_PYR_CTRL_SHD (VPSL_BASE + 0x00094)
|
||||
#define VPSL_PYR_CHN_SHD (VPSL_BASE + 0x00098)
|
||||
#define VPSL_WORKING (VPSL_BASE + 0x000A0)
|
||||
#define VPSL_PIPE_ACK0 (VPSL_BASE + 0x000B0)
|
||||
#define VPSL_PIPE_ACK1 (VPSL_BASE + 0x000B4)
|
||||
#define VPSL_LINE_CNT0 (VPSL_BASE + 0x000C0)
|
||||
#define VPSL_LINE_CNT1 (VPSL_BASE + 0x000C4)
|
||||
#define VPSL_FRAME_CNT (VPSL_BASE + 0x000C8)
|
||||
#define VPSL_PYR_FIFO_DBG (VPSL_BASE + 0x000d0)
|
||||
|
||||
#define VPSL_MI_BASE 0x00001000
|
||||
#define VPSL_MI_CTRL (VPSL_MI_BASE + 0x00000)
|
||||
#define VPSL_MI_WR_INIT (VPSL_MI_BASE + 0x00004)
|
||||
#define VPSL_MI_HURRY_CTRL (VPSL_MI_BASE + 0x00040)
|
||||
#define VPSL_MI_ARQOS_CTRL (VPSL_MI_BASE + 0x00044)
|
||||
#define VPSL_MI_IMSC (VPSL_MI_BASE + 0x00050)
|
||||
#define VPSL_MI_RIS (VPSL_MI_BASE + 0x00054)
|
||||
#define VPSL_MI_MIS (VPSL_MI_BASE + 0x00058)
|
||||
#define VPSL_MI_ICR (VPSL_MI_BASE + 0x0005C)
|
||||
#define VPSL_MI_ISR (VPSL_MI_BASE + 0x00060)
|
||||
#define VPSL_MI_RD_CTRL (VPSL_MI_BASE + 0x00100)
|
||||
#define VPSL_MI_RD_INIT (VPSL_MI_BASE + 0x00104)
|
||||
#define VPSL_MI_RD_START (VPSL_MI_BASE + 0x00108)
|
||||
#define VPSL_MI_RD_Y_BASE (VPSL_MI_BASE + 0x00110)
|
||||
#define VPSL_MI_RD_Y_WIDTH (VPSL_MI_BASE + 0x00114)
|
||||
#define VPSL_MI_RD_Y_HEIGHT (VPSL_MI_BASE + 0x00118)
|
||||
#define VPSL_MI_RD_Y_STRIDE (VPSL_MI_BASE + 0x0011C)
|
||||
#define VPSL_MI_RD_Y_BASE_SHD (VPSL_MI_BASE + 0x00130)
|
||||
#define VPSL_MI_RD_Y_WIDTH_SHD (VPSL_MI_BASE + 0x00138)
|
||||
#define VPSL_MI_RD_Y_HEIGHT_SHD (VPSL_MI_BASE + 0x0013C)
|
||||
#define VPSL_MI_CHN0_WR_CTRL (VPSL_MI_BASE + 0x00200)
|
||||
#define VPSL_MI_CHN0_WR_BASE (VPSL_MI_BASE + 0x00210)
|
||||
#define VPSL_MI_CHN0_WR_SIZE (VPSL_MI_BASE + 0x00224)
|
||||
#define VPSL_MI_CHN0_WR_STRIDE (VPSL_MI_BASE + 0x00228)
|
||||
#define VPSL_MI_CHN0_WR_BASE_SHD (VPSL_MI_BASE + 0x00230)
|
||||
#define VPSL_MI_CHN0_WR_END_ADDR (VPSL_MI_BASE + 0x00234)
|
||||
#define VPSL_MI_CHN1_WR_CTRL (VPSL_MI_BASE + 0x00300)
|
||||
#define VPSL_MI_CHN1_WR_BASE (VPSL_MI_BASE + 0x00310)
|
||||
#define VPSL_MI_CHN1_WR_SIZE (VPSL_MI_BASE + 0x00324)
|
||||
#define VPSL_MI_CHN1_WR_STRIDE (VPSL_MI_BASE + 0x00328)
|
||||
#define VPSL_MI_CHN1_WR_BASE_SHD (VPSL_MI_BASE + 0x00330)
|
||||
#define VPSL_MI_CHN1_WR_END_ADDR (VPSL_MI_BASE + 0x00334)
|
||||
#define VPSL_MI_CHN2_WR_CTRL (VPSL_MI_BASE + 0x00400)
|
||||
#define VPSL_MI_CHN2_WR_BASE (VPSL_MI_BASE + 0x00410)
|
||||
#define VPSL_MI_CHN2_WR_SIZE (VPSL_MI_BASE + 0x00424)
|
||||
#define VPSL_MI_CHN2_WR_STRIDE (VPSL_MI_BASE + 0x00428)
|
||||
#define VPSL_MI_CHN2_WR_BASE_SHD (VPSL_MI_BASE + 0x00430)
|
||||
#define VPSL_MI_CHN2_WR_END_ADDR (VPSL_MI_BASE + 0x00434)
|
||||
#define VPSL_MI_CHN3_WR_CTRL (VPSL_MI_BASE + 0x00500)
|
||||
#define VPSL_MI_CHN3_WR_BASE (VPSL_MI_BASE + 0x00510)
|
||||
#define VPSL_MI_CHN3_WR_SIZE (VPSL_MI_BASE + 0x00524)
|
||||
#define VPSL_MI_CHN3_WR_STRIDE (VPSL_MI_BASE + 0x00528)
|
||||
#define VPSL_MI_CHN3_WR_BASE_SHD (VPSL_MI_BASE + 0x00530)
|
||||
#define VPSL_MI_CHN3_WR_END_ADDR (VPSL_MI_BASE + 0x00534)
|
||||
#define VPSL_MI_CHN4_WR_CTRL (VPSL_MI_BASE + 0x00600)
|
||||
#define VPSL_MI_CHN4_WR_BASE (VPSL_MI_BASE + 0x00610)
|
||||
#define VPSL_MI_CHN4_WR_SIZE (VPSL_MI_BASE + 0x00624)
|
||||
#define VPSL_MI_CHN4_WR_STRIDE (VPSL_MI_BASE + 0x00628)
|
||||
#define VPSL_MI_CHN4_WR_BASE_SHD (VPSL_MI_BASE + 0x00630)
|
||||
#define VPSL_MI_CHN4_WR_END_ADDR (VPSL_MI_BASE + 0x00634)
|
||||
#define VPSL_MI_CHN5_WR_CTRL (VPSL_MI_BASE + 0x00700)
|
||||
#define VPSL_MI_CHN5_WR_BASE (VPSL_MI_BASE + 0x00710)
|
||||
#define VPSL_MI_CHN5_WR_SIZE (VPSL_MI_BASE + 0x00724)
|
||||
#define VPSL_MI_CHN5_WR_STRIDE (VPSL_MI_BASE + 0x00728)
|
||||
#define VPSL_MI_CHN5_WR_BASE_SHD (VPSL_MI_BASE + 0x00730)
|
||||
#define VPSL_MI_CHN5_WR_END_ADDR (VPSL_MI_BASE + 0x00734)
|
||||
#define VPSL_MI_CHN6_WR_CTRL (VPSL_MI_BASE + 0x00800)
|
||||
#define VPSL_MI_CHN6_WR_BASE (VPSL_MI_BASE + 0x00810)
|
||||
#define VPSL_MI_CHN6_WR_SIZE (VPSL_MI_BASE + 0x00824)
|
||||
#define VPSL_MI_CHN6_WR_STRIDE (VPSL_MI_BASE + 0x00828)
|
||||
#define VPSL_MI_CHN6_WR_BASE_SHD (VPSL_MI_BASE + 0x00830)
|
||||
#define VPSL_MI_CHN6_WR_END_ADDR (VPSL_MI_BASE + 0x00834)
|
||||
#define VPSL_MI_CHN7_WR_CTRL (VPSL_MI_BASE + 0x00900)
|
||||
#define VPSL_MI_CHN7_WR_BASE (VPSL_MI_BASE + 0x00910)
|
||||
#define VPSL_MI_CHN7_WR_SIZE (VPSL_MI_BASE + 0x00924)
|
||||
#define VPSL_MI_CHN7_WR_STRIDE (VPSL_MI_BASE + 0x00928)
|
||||
#define VPSL_MI_CHN7_WR_BASE_SHD (VPSL_MI_BASE + 0x00930)
|
||||
#define VPSL_MI_CHN7_WR_END_ADDR (VPSL_MI_BASE + 0x00934)
|
||||
#define VPSL_MI_CHN8_WR_CTRL (VPSL_MI_BASE + 0x00a00)
|
||||
#define VPSL_MI_CHN8_WR_BASE (VPSL_MI_BASE + 0x00a10)
|
||||
#define VPSL_MI_CHN8_WR_SIZE (VPSL_MI_BASE + 0x00a24)
|
||||
#define VPSL_MI_CHN8_WR_STRIDE (VPSL_MI_BASE + 0x00a28)
|
||||
#define VPSL_MI_CHN8_WR_BASE_SHD (VPSL_MI_BASE + 0x00a30)
|
||||
#define VPSL_MI_CHN8_WR_END_ADDR (VPSL_MI_BASE + 0x00a34)
|
||||
#define VPSL_MI_CHN9_WR_CTRL (VPSL_MI_BASE + 0x00b00)
|
||||
#define VPSL_MI_CHN9_WR_BASE (VPSL_MI_BASE + 0x00b10)
|
||||
#define VPSL_MI_CHN9_WR_SIZE (VPSL_MI_BASE + 0x00b24)
|
||||
#define VPSL_MI_CHN9_WR_STRIDE (VPSL_MI_BASE + 0x00b28)
|
||||
#define VPSL_MI_CHN9_WR_BASE_SHD (VPSL_MI_BASE + 0x00b30)
|
||||
#define VPSL_MI_CHN9_WR_END_ADDR (VPSL_MI_BASE + 0x00b34)
|
||||
#define VPSL_MI_CHN10_WR_CTRL (VPSL_MI_BASE + 0x00c00)
|
||||
#define VPSL_MI_CHN10_WR_BASE (VPSL_MI_BASE + 0x00c10)
|
||||
#define VPSL_MI_CHN10_WR_SIZE (VPSL_MI_BASE + 0x00c24)
|
||||
#define VPSL_MI_CHN10_WR_STRIDE (VPSL_MI_BASE + 0x00c28)
|
||||
#define VPSL_MI_CHN10_WR_BASE_SHD (VPSL_MI_BASE + 0x00c30)
|
||||
#define VPSL_MI_CHN10_WR_END_ADDR (VPSL_MI_BASE + 0x00c34)
|
||||
|
||||
#define VPSL_PYR_YRAW_MODE(x) ((x) & 0x3)
|
||||
#define VPSL_PYR_SIGMA_EN BIT(2)
|
||||
#define VPSL_PYR_RAW_MODE BIT(4)
|
||||
#define VPSL_PYR_GAIN_LEFTSHIFT(x) (((x) & 0x7) << 8)
|
||||
#define VPSL_PYR_BLK_SIG(x) (((x) & 0xff) << 16)
|
||||
#define VPSL_PYR_TBL_RD_ONLY BIT(28)
|
||||
#define VPSL_PYR_CHN_ADAPT_DIS BIT(29)
|
||||
#define VPSL_PYR_ERR_CLR_P BIT(30)
|
||||
#define VPSL_PYR_TBL_CLR_P BIT(31)
|
||||
|
||||
#define VPSL_CHN0_EN BIT(0)
|
||||
#define VPSL_CHN1_EN BIT(1)
|
||||
#define VPSL_CHN2_EN BIT(2)
|
||||
#define VPSL_CHN3_EN BIT(3)
|
||||
#define VPSL_CHN4_EN BIT(4)
|
||||
#define VPSL_CHN5_EN BIT(5)
|
||||
#define VPSL_CHN6_EN BIT(6)
|
||||
#define VPSL_CHN7_EN BIT(7)
|
||||
#define VPSL_CHN8_EN BIT(8)
|
||||
#define VPSL_CHN9_EN BIT(9)
|
||||
#define VPSL_CHN10_EN BIT(10)
|
||||
|
||||
#define VPSL_CFG_FORCE_UPD BIT(0)
|
||||
#define VPSL_CFG_GEN_UPD BIT(1)
|
||||
#define VPSL_YRAW_CHN_FORCE_UPD BIT(4)
|
||||
#define VPSL_SIGMA_CHN_FORCE_UPD BIT(5)
|
||||
|
||||
#define VPSL_YRAW_CLK_EN BIT(0)
|
||||
#define VPSL_SIGMA_CLK_EN BIT(1)
|
||||
#define VPSL_MI_CLK_EN BIT(31)
|
||||
|
||||
#define VPSL_YRAW_CKG_DIS BIT(0)
|
||||
#define VPSL_SIGMA_CKG_DIS BIT(1)
|
||||
#define VPSL_MI_CHN0_CKG_DIS BIT(16)
|
||||
#define VPSL_MI_CHN1_CKG_DIS BIT(17)
|
||||
#define VPSL_MI_CHN2_CKG_DIS BIT(18)
|
||||
#define VPSL_MI_CHN3_CKG_DIS BIT(19)
|
||||
#define VPSL_MI_CHN4_CKG_DIS BIT(20)
|
||||
#define VPSL_MI_CHN5_CKG_DIS BIT(21)
|
||||
#define VPSL_MI_CHN6_CKG_DIS BIT(22)
|
||||
#define VPSL_MI_CHN7_CKG_DIS BIT(23)
|
||||
#define VPSL_MI_CHN8_CKG_DIS BIT(24)
|
||||
#define VPSL_MI_CHN9_CKG_DIS BIT(25)
|
||||
#define VPSL_MI_CHN10_CKG_DIS BIT(26)
|
||||
#define VPSL_MI_RD_CKG_DIS BIT(31)
|
||||
|
||||
#define VPSL_GLB_SOFT_RST BIT(0)
|
||||
#define VPSL_RST_PROTECT_DIS BIT(30)
|
||||
#define VPSL_SAFETY_DONE_CLR BIT(31)
|
||||
|
||||
#define VPSL_ISP2VPSL_FRM_ST BIT(0)
|
||||
#define VPSL_YRAW_IN_FRM_END BIT(4)
|
||||
#define VPSL_YRAW_IN_CFG_IRQ BIT(5)
|
||||
#define VPSL_YRAW_FRM_END BIT(6)
|
||||
#define VPSL_SIGMA_IN_FRM_END BIT(8)
|
||||
#define VPSL_SIGMA_IN_CFG_IRQ BIT(9)
|
||||
#define VPSL_SIGMA_FRM_END BIT(10)
|
||||
#define VPSL_SIGMA_GAIN_FULL_ERR BIT(31)
|
||||
|
||||
#define VPSL_MI_WR_INIT_BASE_EN BIT(4)
|
||||
#define VPSL_MI_WR_INIT_OFFSET_EN BIT(5)
|
||||
#define VPSL_MI_WR_FIFO_DIS BIT(24)
|
||||
#define VPSL_MI_WR_GLB_EN_DIS BIT(25)
|
||||
#define VPSL_MI_WR_ID_POLL_CLR BIT(26)
|
||||
#define VPSL_MI_WR_ID_POLL_DIS BIT(27)
|
||||
|
||||
#define VPSL_MI_FORCE_UPD BIT(0)
|
||||
#define VPSL_MI_CHN0_SELF_UPD BIT(4)
|
||||
#define VPSL_MI_CHN1_SELF_UPD BIT(5)
|
||||
#define VPSL_MI_CHN2_SELF_UPD BIT(6)
|
||||
#define VPSL_MI_CHN3_SELF_UPD BIT(7)
|
||||
#define VPSL_MI_CHN4_SELF_UPD BIT(8)
|
||||
#define VPSL_MI_CHN5_SELF_UPD BIT(9)
|
||||
#define VPSL_MI_CHN6_SELF_UPD BIT(10)
|
||||
#define VPSL_MI_CHN7_SELF_UPD BIT(11)
|
||||
#define VPSL_MI_CHN8_SELF_UPD BIT(12)
|
||||
#define VPSL_MI_CHN9_SELF_UPD BIT(13)
|
||||
#define VPSL_MI_CHN10_SELF_UPD BIT(14)
|
||||
#define VPSL_ITSELF_FORCE_PRO_DIS BIT(31)
|
||||
|
||||
#define VPSL_CHN_WR_AUTO_UPD BIT(1)
|
||||
#define VPSL_CHN_BURST_LEN(x) (((x) & 0x3) << 8)
|
||||
#define VPSL_CHN_WR_EN_SHD BIT(30)
|
||||
#define VPSL_CHN_WORKING BIT(31)
|
||||
|
||||
#define VPSL_MI_CHN0_END BIT(0)
|
||||
#define VPSL_MI_CHN1_END BIT(1)
|
||||
#define VPSL_MI_CHN2_END BIT(2)
|
||||
#define VPSL_MI_CHN3_END BIT(3)
|
||||
#define VPSL_MI_CHN4_END BIT(4)
|
||||
#define VPSL_MI_CHN5_END BIT(5)
|
||||
#define VPSL_MI_CHN6_END BIT(6)
|
||||
#define VPSL_MI_CHN7_END BIT(7)
|
||||
#define VPSL_MI_CHN8_END BIT(8)
|
||||
#define VPSL_MI_CHN9_END BIT(9)
|
||||
#define VPSL_MI_CHN10_END BIT(10)
|
||||
#define VPSL_MI_READ_END BIT(16)
|
||||
#define VPSL_BUS_ERR BIT(28)
|
||||
#define VPSL_MI_SIGMA_ALL_END BIT(30)
|
||||
#define VPSL_MI_YRAW_ALL_END BIT(31)
|
||||
|
||||
#define VPSL_SW_REG_SIZE 0x2000
|
||||
#define VPSL_SW_MAX_SIZE (VPSL_SW_REG_SIZE * 2)
|
||||
|
||||
static inline void vpsl_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct)
|
||||
{
|
||||
void __iomem *base = dev->hw_dev->vpsl_base_addr;
|
||||
u32 *mem = dev->sw_vpsl_base_addr + reg;
|
||||
u32 *flag = dev->sw_vpsl_base_addr + reg + VPSL_SW_REG_SIZE;
|
||||
|
||||
*mem = val;
|
||||
*flag = SW_REG_CACHE;
|
||||
if (dev->hw_dev->is_single || is_direct) {
|
||||
*flag = SW_REG_CACHE_SYNC;
|
||||
writel(val, base + reg);
|
||||
}
|
||||
}
|
||||
|
||||
static inline u32 vpsl_read(struct rkisp_device *dev, u32 reg, bool is_direct)
|
||||
{
|
||||
void __iomem *base = dev->hw_dev->vpsl_base_addr;
|
||||
u32 val;
|
||||
|
||||
if (dev->hw_dev->is_single || is_direct)
|
||||
val = readl(base + reg);
|
||||
else
|
||||
val = *(u32 *)(dev->sw_vpsl_base_addr + reg);
|
||||
return val;
|
||||
}
|
||||
#endif
|
||||
@@ -430,10 +430,11 @@ struct rkisp_aiisp_ev_info {
|
||||
int sequence;
|
||||
int height;
|
||||
|
||||
/* bnr front end */
|
||||
int iir_index;
|
||||
int gain_index;
|
||||
/* bnr back end */
|
||||
int aipre_gain_index;
|
||||
int vpsl_index;
|
||||
|
||||
int aiisp_index;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
@@ -443,7 +444,11 @@ struct rkisp_aiisp_st {
|
||||
|
||||
int iir_index;
|
||||
int gain_index;
|
||||
|
||||
int aiisp_index;
|
||||
|
||||
int aipre_gain_index;
|
||||
int vpsl_index;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/* struct rkisp_aiisp_cfg
|
||||
@@ -457,6 +462,9 @@ struct rkisp_aiisp_cfg {
|
||||
int rd_linecnt;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#define VPSL_YRAW_CHN_MAX 6
|
||||
#define VPSL_SIG_CHN_MAX 5
|
||||
|
||||
struct rkisp_bnr_buf_info {
|
||||
struct rkisp_buf_info iir;
|
||||
union {
|
||||
@@ -465,6 +473,24 @@ struct rkisp_bnr_buf_info {
|
||||
struct rkisp_buf_info gain;
|
||||
__u8 iirsparse_en;
|
||||
} v39;
|
||||
struct {
|
||||
struct rkisp_buf_info ds;
|
||||
struct rkisp_buf_info wgt;
|
||||
|
||||
struct rkisp_buf_info aiisp;
|
||||
struct rkisp_buf_info gain;
|
||||
struct rkisp_buf_info aipre_gain;
|
||||
struct rkisp_buf_info vpsl;
|
||||
__u8 iir_rw_fmt;
|
||||
__u8 gain_mode;
|
||||
__u8 yraw_sel;
|
||||
/* yraw ds_2x2 to ds_64x64 buf offset and stride */
|
||||
__u32 vpsl_yraw_offs[VPSL_YRAW_CHN_MAX];
|
||||
__u32 vpsl_yraw_stride[VPSL_YRAW_CHN_MAX];
|
||||
/* sigma ds_2x2 to ds_32x32 buf offset and stride */
|
||||
__u32 vpsl_sig_offs[VPSL_SIG_CHN_MAX];
|
||||
__u32 vpsl_sig_stride[VPSL_SIG_CHN_MAX];
|
||||
} v35;
|
||||
} u;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
|
||||
@@ -157,6 +157,7 @@
|
||||
#define ISP35_BAY3D_FILT_COEFF_NUM 6
|
||||
|
||||
#define ISP35_AI_SIGMA_NUM 33
|
||||
#define ISP35_VPSL_SIGMA_NUM 81
|
||||
|
||||
#define ISP35_SHARP_X_NUM ISP33_SHARP_X_NUM
|
||||
#define ISP35_SHARP_Y_NUM ISP33_SHARP_Y_NUM
|
||||
@@ -625,7 +626,7 @@ struct isp35_ai_cfg {
|
||||
__u16 aiisp_sigma_y[ISP35_AI_SIGMA_NUM];
|
||||
/* AIPRE_NL_PRE */
|
||||
__u8 aipre_scale;
|
||||
__u8 aipre_zp;
|
||||
__s8 aipre_zp;
|
||||
__u16 aipre_black_lvl;
|
||||
/* AIPRE_GAIN_PARA */
|
||||
__u8 aipre_gain_alpha;
|
||||
@@ -635,7 +636,7 @@ struct isp35_ai_cfg {
|
||||
__u16 aipre_sigma_y[ISP35_AI_SIGMA_NUM];
|
||||
/* AIPRE_NOISE0 */
|
||||
__u8 aipre_noise_mot_offset;
|
||||
__u8 aipre_noise_mot_gain;
|
||||
__s8 aipre_noise_mot_gain;
|
||||
__u16 aipre_noise_luma_offset;
|
||||
/* AIPRE_NOISE1 */
|
||||
__u16 aipre_noise_luma_gain;
|
||||
@@ -644,6 +645,15 @@ struct isp35_ai_cfg {
|
||||
/* AIPRE_NOISE2 */
|
||||
__u8 aipre_nar_manual;
|
||||
__u8 aipre_nar_manual_alpha;
|
||||
|
||||
/* VPSL_PYR_CTRL */
|
||||
__u8 pyr_yraw_mode;
|
||||
__u8 pyr_sigma_en;
|
||||
__u8 pyr_yraw_sel;
|
||||
__u8 pyr_gain_leftshift;
|
||||
__u8 pyr_blacklvl_sig;
|
||||
/* VPSL_PYR_SIGMA_LUT */
|
||||
__u8 pyr_sigma_y[ISP35_VPSL_SIGMA_NUM];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct isp35_ynr_cfg {
|
||||
@@ -1739,7 +1749,14 @@ struct isp35_stat {
|
||||
struct isp33_hist_stat hist;
|
||||
struct isp35_awbsync_stat awbsync;
|
||||
struct isp32_info2ddr_stat info2ddr;
|
||||
|
||||
int buf_aiawb_index;
|
||||
int buf_bay3d_iir_index;
|
||||
int buf_bay3d_ds_index;
|
||||
int buf_bay3d_wgt_index;
|
||||
int buf_gain_index;
|
||||
int buf_aipre_gain_index;
|
||||
int buf_vpsl_index;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct rkisp35_stat_buffer {
|
||||
|
||||
Reference in New Issue
Block a user