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ARM64: rockchip: rk3399 reorder codes in rk3399-cdn-dp

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Sync with upstream codes.

Change-Id: Ic5306bdf16125e46892b5a85339afec67ad85482
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This commit is contained in:
Jianqun Xu
2018-07-26 16:18:40 +08:00
committed by Tao Huang
parent 6bc17c0755
commit d6f0e7b388
1 changed files with 2 additions and 2 deletions
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4
arch/arm64/boot/dts/rockchip/rk3399.dtsi
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@@ -465,11 +465,11 @@
compatible = "rockchip,rk3399-cdn-dp";
reg = <0x0 0xfec00000 0x0 0x100000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&cru SCLK_DP_CORE>;
assigned-clock-rates = <100000000>;
clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
<&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
clock-names = "core-clk", "pclk", "spdif", "grf";
assigned-clocks = <&cru SCLK_DP_CORE>;
assigned-clock-rates = <100000000>;
power-domains = <&power RK3399_PD_HDCP>;
phys = <&tcphy0_dp>, <&tcphy1_dp>;
resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,