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clk: rockchip: avoid unintentional integer overflow in rockchip_rk3588_pll_recalc_rate()

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Fixes: 58c1fa2ef2 ("clk: rockchip: add pll type for RK3588")
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I840458595475e9e1bb6df74453829ea22dd2d729
This commit is contained in:
Jianqun Xu
2022-06-16 18:17:49 +08:00
committed by Tao Huang
parent 8704b56415
commit d741b100b4
1 changed files with 4 additions and 1 deletions
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5
drivers/clk/rockchip/clk-pll.c
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@@ -1329,6 +1329,8 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw,
return pll->scaling;
rockchip_rk3588_pll_get_params(pll, &cur);
if (cur.p == 0)
return prate;
rate64 *= cur.m;
do_div(rate64, cur.p);
@@ -1337,7 +1339,8 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw,
/* fractional mode */
u64 frac_rate64 = prate * cur.k;
postdiv = cur.p * 65536;
postdiv = cur.p;
postdiv *= 65536;
do_div(frac_rate64, postdiv);
rate64 += frac_rate64;
}