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media: rockchip: isp: raw data dma read/write default to burst16*4

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Change-Id: I4814dacdc61f824c87dcf64caa6ff9320406800f
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
Cai YiWei
2021-12-03 17:38:05 +08:00
committed by Tao Huang
parent 9733c0fe9d
commit dd7a2a2505
2 changed files with 34 additions and 0 deletions
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12
drivers/media/platform/rockchip/isp/hw.c
View File

@@ -758,6 +758,18 @@ static int enable_sys_clk(struct rkisp_hw_dev *dev)
writel(0, dev->base_addr + CIF_ISP_CSI0_MASK1);
writel(0, dev->base_addr + CIF_ISP_CSI0_MASK2);
writel(0, dev->base_addr + CIF_ISP_CSI0_MASK3);
} else if (dev->isp_ver == ISP_V30) {
writel(ISP3X_RAWX_RD_BURST_LEN16 |
ISP3X_RAWX_WR_BURST_LEN16 |
ISP3X_RD_RAWX_GROUP_MODE_X4 |
ISP3X_WR_RAWX_GROUP_MODE_X4,
dev->base_addr + ISP3X_MI_RD_CTRL2);
if (dev->is_unite)
writel(ISP3X_RAWX_RD_BURST_LEN16 |
ISP3X_RAWX_WR_BURST_LEN16 |
ISP3X_RD_RAWX_GROUP_MODE_X4 |
ISP3X_WR_RAWX_GROUP_MODE_X4,
dev->base_next_addr + ISP3X_MI_RD_CTRL2);
}
return 0;

22
drivers/media/platform/rockchip/isp/regs_v3x.h
View File

@@ -1684,6 +1684,28 @@
#define ISP3X_DBR_ST_MODE BIT(30)
#define ISP3X_DBR_ST BIT(31)
/* MI_RD_CTRL2 */
#define ISP3X_RAWX_RD_BURST_LEN_MASK GENMASK(23, 22)
#define ISP3X_RAWX_WR_BURST_LEN_MASK GENMASK(21, 20)
#define ISP3X_RD_RAWX_GROUP_MODE_MASK GENMASK(19, 18)
#define ISP3X_WR_RAWX_GROUP_MODE_MASK GENMASK(17, 16)
#define ISP3X_RAWX_RD_BURST_LEN4 0
#define ISP3X_RAWX_RD_BURST_LEN8 BIT(22)
#define ISP3X_RAWX_RD_BURST_LEN16 BIT(23)
#define ISP3X_RAWX_RD_BURST_LEN2 (0x3 << 22)
#define ISP3X_RAWX_WR_BURST_LEN4 0
#define ISP3X_RAWX_WR_BURST_LEN8 BIT(20)
#define ISP3X_RAWX_WR_BURST_LEN16 BIT(21)
#define ISP3X_RAWX_WR_BURST_LEN2 (0x3 << 20)
#define ISP3X_RD_RAWX_GROUP_MODE_X4 0
#define ISP3X_RD_RAWX_GROUP_MODE_X3 BIT(18)
#define ISP3X_RD_RAWX_GROUP_MODE_X2 BIT(19)
#define ISP3X_RD_RAWX_GROUP_MODE_X1 (0x3 << 18)
#define ISP3X_WR_RAWX_GROUP_MODE_X4 0
#define ISP3X_WR_RAWX_GROUP_MODE_X3 BIT(16)
#define ISP3X_WR_RAWX_GROUP_MODE_X2 BIT(17)
#define ISP3X_WR_RAWX_GROUP_MODE_X1 (0x3 << 16)
/* BP_WR_CTRL */
#define ISP3X_BP_ENABLE BIT(0)
#define ISP3X_BP_AUTO_UPD BIT(1)