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media: i2c: rk628: set CPLL_REF_CLK to 1194M

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Fix CTS HF2-6/HF2-23

Signed-off-by: Chen Shunqing <csq@rock-chips.com>
Change-Id: I90f56fbeb6917841208ac9b6b82ec2fdb3566354
This commit is contained in:
Chen Shunqing
2024-07-18 16:39:00 +08:00
committed by Tao Huang
parent 8826fbcc1d
commit dd812e1c19
5 changed files with 6 additions and 16 deletions
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2
drivers/media/i2c/rk628/rk628_bt1120_v4l2.c
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@@ -335,7 +335,6 @@ static void rk628_hdmirx_plugout(struct v4l2_subdev *sd)
rk628_hdmirx_hpd_ctrl(sd, false);
rk628_hdmirx_inno_phy_power_off(sd);
rk628_hdmirx_verisyno_phy_power_off(bt1120->rk628);
rk628_clk_set_rate(bt1120->rk628, CGU_CLK_CPLL, CPLL_REF_CLK);
}
static void rk628_hdmirx_config_all(struct v4l2_subdev *sd)
@@ -1967,6 +1966,7 @@ static int rk628_bt1120_probe(struct i2c_client *client,
rk628_bt1120_power_on(bt1120);
rk628_cru_initialize(rk628);
rk628_clk_set_rate(rk628, CGU_CLK_CPLL, CPLL_REF_CLK);
rk628_version_parse(rk628);

3
drivers/media/i2c/rk628/rk628_cru.h
View File

@@ -195,7 +195,8 @@
#define RGU_TXESC 30
#define RGU_CSI1 31
#define CPLL_REF_CLK 1188000000
/* CTS HF2-6/HF2-23 test frequency +/-0.5%, (1188M * 1.005) */
#define CPLL_REF_CLK 1194000000
unsigned long rk628_clk_get_rate(struct rk628 *rk628, unsigned int id);
int rk628_clk_set_rate(struct rk628 *rk628, unsigned int id,

2
drivers/media/i2c/rk628/rk628_csi_v4l2.c
View File

@@ -486,7 +486,6 @@ static void rk628_hdmirx_plugout(struct v4l2_subdev *sd)
rk628_hdmirx_hpd_ctrl(sd, false);
rk628_hdmirx_inno_phy_power_off(sd);
rk628_hdmirx_verisyno_phy_power_off(csi->rk628);
rk628_clk_set_rate(csi->rk628, CGU_CLK_CPLL, CPLL_REF_CLK);
}
static void rk628_hdmirx_config_all(struct v4l2_subdev *sd)
@@ -3374,6 +3373,7 @@ static int rk628_csi_probe(struct i2c_client *client,
rk628_csi_power_on(csi);
rk628_cru_initialize(csi->rk628);
rk628_clk_set_rate(rk628, CGU_CLK_CPLL, CPLL_REF_CLK);
rk628_version_parse(rk628);

12
drivers/media/i2c/rk628/rk628_hdmirx.c
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@@ -1703,7 +1703,6 @@ int rk628_hdmirx_get_timings(struct rk628 *rk628,
{
int i, cnt = 0, ret = 0;
u32 last_w, last_h;
u32 val;
u8 last_fmt;
struct v4l2_bt_timings *bt = &timings->bt;
@@ -1747,17 +1746,6 @@ int rk628_hdmirx_get_timings(struct rk628 *rk628,
ret = -EINVAL;
}
if (rk628->version >= RK628F_VERSION) {
val = DIV_ROUND_CLOSEST_ULL(1188000000, bt->pixelclock);
val *= bt->pixelclock;
if (bt->pixelclock > 594000000) {
/* set pll rate according hdmirx tmds clk */
rk628_clk_set_rate(rk628, CGU_CLK_CPLL, val);
rk628_dbg(rk628, "set CPLL to %d\n", val);
msleep(50);
}
}
return ret;
}
EXPORT_SYMBOL(rk628_hdmirx_get_timings);

3
drivers/media/i2c/rk628/rk628_hdmirx.h
View File

@@ -14,6 +14,7 @@
#include <media/v4l2-dv-timings.h>
#include "rk628.h"
#include "rk628_cru.h"
/* --------- EDID and HDCP KEY ------- */
#define EDID_BASE 0x000a0000
@@ -440,7 +441,7 @@
#define HDMIRX_GET_TIMING_CNT 20
#define HDMIRX_MODETCLK_CNT_NUM 1000
#define HDMIRX_MODETCLK_HZ 49500000
#define HDMIRX_MODETCLK_HZ (CPLL_REF_CLK / 24)
#define EDID_NUM_BLOCKS_MAX 2
#define EDID_BLOCK_SIZE 128