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drm/rockchip: dsi: add rk312x support
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> Change-Id: Iedf823a62e28b760444f064d6ccfed6a4fe5f36c
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@@ -149,6 +149,11 @@
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#define PX30_DSI_TURNDISABLE BIT(5)
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#define PX30_DSI_LCDC_SEL BIT(0)
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#define RK3128_GRF_LVDS_CON0 0x0150
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#define RK3128_DSI_FORCETXSTOPMODE (0xf << 10)
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#define RK3128_DSI_FORCERXMODE (0x1 << 9)
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#define RK3128_DSI_TURNDISABLE (0x1 << 8)
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#define RK3288_GRF_SOC_CON6 0x025c
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#define RK3288_DSI0_LCDC_SEL BIT(6)
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#define RK3288_DSI1_LCDC_SEL BIT(9)
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@@ -213,6 +218,7 @@ enum {
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enum soc_type {
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PX30,
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RK3128,
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RK3288,
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RK3399,
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RK3568,
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@@ -1283,6 +1289,21 @@ static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
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{ /* sentinel */ }
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};
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static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = {
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{
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.reg = 0x10110000,
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.lanecfg1_grf_reg = RK3128_GRF_LVDS_CON0,
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.lanecfg1 = HIWORD_UPDATE(0, RK3128_DSI_TURNDISABLE |
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RK3128_DSI_FORCETXSTOPMODE |
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RK3128_DSI_FORCERXMODE),
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.flags = DW_MIPI_NEEDS_HCLK,
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.max_data_lanes = 4,
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.max_bit_rate_per_lane = 1000000000UL,
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.soc_type = RK3128,
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},
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{ /* sentinel */ }
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};
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static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
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{
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.reg = 0xff960000,
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@@ -1407,6 +1428,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
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{
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.compatible = "rockchip,px30-mipi-dsi",
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.data = &px30_chip_data,
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}, {
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.compatible = "rockchip,rk3128-mipi-dsi",
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.data = &rk3128_chip_data,
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}, {
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.compatible = "rockchip,rk3288-mipi-dsi",
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.data = &rk3288_chip_data,
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