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clk: rockchip: rk3562: change pll to slow mode before power down

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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I7ee6d2478bc012bf70ca061738534ed57d1612f0
This commit is contained in:
Finley Xiao
2023-02-09 13:03:32 +08:00
committed by Tao Huang
parent 0ce21e2477
commit ddea4b4025
1 changed files with 8 additions and 0 deletions
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8
drivers/clk/rockchip/clk-pll.c
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@@ -647,17 +647,25 @@ static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate,
static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
struct clk_mux *pll_mux = &pll->pll_mux;
writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
pll->reg_base + RK3036_PLLCON(1));
rockchip_rk3036_pll_wait_lock(pll);
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
return 0;
}
static void rockchip_rk3036_pll_disable(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
struct clk_mux *pll_mux = &pll->pll_mux;
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
RK3036_PLLCON1_PWRDOWN, 0),