cec: sm1 send bus level check fail [1/1]

PD#SWPL-17583

Problem:
cec send msg, cec bus level check fail.
the register define is not right.

Solution:
cec bus input register is PREG_PAD_GPIO3_I.

Verify:
SM1

Change-Id: I2eb49cab79a0141141ae3fafb704239c2c779485
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
This commit is contained in:
Yong Qin
2019-12-09 17:34:17 +08:00
committed by Luke Go
parent 630b68335a
commit de6cc6ebe2
2 changed files with 6 additions and 6 deletions

View File

@@ -3536,7 +3536,7 @@ static const struct cec_platform_data_s cec_g12b_data = {
static const struct cec_platform_data_s cec_txl_data = {
.chip_id = CEC_CHIP_TXL,
.line_reg = 0,
.line_reg = 0,/*line_reg=0:AO_GPIO_I*/
.line_bit = 7,
.ee_to_ao = 0,
.ceca_sts_reg = 0,
@@ -3547,7 +3547,7 @@ static const struct cec_platform_data_s cec_txl_data = {
static const struct cec_platform_data_s cec_tl1_data = {
.chip_id = CEC_CHIP_TL1,
.line_reg = 0,
.line_reg = 0,/*line_reg=0:AO_GPIO_I*/
.line_bit = 10,
.ee_to_ao = 1,
.ceca_sts_reg = 1,
@@ -3558,8 +3558,8 @@ static const struct cec_platform_data_s cec_tl1_data = {
static const struct cec_platform_data_s cec_sm1_data = {
.chip_id = CEC_CHIP_SM1,
.line_reg = 1,
.line_bit = 10,
.line_reg = 1,/*line_reg=1:PREG_PAD_GPIO3_I*/
.line_bit = 3,
.ee_to_ao = 1,
.ceca_sts_reg = 1,
.ceca_ver = CECA_VER_1,
@@ -3569,7 +3569,7 @@ static const struct cec_platform_data_s cec_sm1_data = {
static const struct cec_platform_data_s cec_tm2_data = {
.chip_id = CEC_CHIP_TM2,
.line_reg = 0,
.line_reg = 0,/*line_reg=0:AO_GPIO_I*/
.line_bit = 10,
.ee_to_ao = 1,
.ceca_sts_reg = 1,

View File

@@ -18,7 +18,7 @@
#ifndef __AO_CEC_H__
#define __AO_CEC_H__
#define CEC_DRIVER_VERSION "2019/12/01:finetune ARB time, cause cts 9.6.1\n"
#define CEC_DRIVER_VERSION "2019/12/09:sm1 bus check reg define err\n"
#define CEC_FRAME_DELAY msecs_to_jiffies(400)
#define CEC_DEV_NAME "cec"