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clk: rockchip: rk3588: add PLL 1.1G parameter

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1.1G may used for PPLL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I77b539ca94a5a51efa34ad2ea4b355b27b21ed0b
This commit is contained in:
Kever Yang
2022-04-19 15:27:37 +08:00
parent b9c18b2b3a
commit de7d060208
1 changed files with 1 additions and 0 deletions
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drivers/clk/rockchip/clk-rk3588.c
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@@ -75,6 +75,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
RK3588_PLL_RATE(1320000000, 2, 220, 1, 0),
RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),
RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
RK3588_PLL_RATE(983040000, 4, 655, 2, 23592),