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vpu: add tm2 support [1/1]

Browse Source 
PD#SWPL-6397

Problem:
tm2 is a new chip

Solution:
add vpu driver support for tm2

Verify:
pxp

Change-Id: I19275c513b68fba8feced37f1ff8fca9bf48d395
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
This commit is contained in:
Evoke Zhang
2019-03-29 15:53:06 +08:00
committed by Luke Go
parent 47408422ea
commit e04a70e982
5 changed files with 173 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

45
drivers/amlogic/media/common/vpu/vpu.c
View File

@@ -40,7 +40,8 @@
/* v05: add txl support */
/* v20180925: add tl1 support */
/* v20190314: add sm1 support */
#define VPU_VERION "v20190314"
/* v20190329: add tm2 support */
#define VPU_VERION "v20190329"
int vpu_debug_print_flag;
static spinlock_t vpu_mem_lock;
@@ -1256,6 +1257,7 @@ static struct vpu_data_s vpu_data_gxb = {
.module_init_table_cnt = 0,
.module_init_table = NULL,
.hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
.hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
};
@@ -1282,6 +1284,7 @@ static struct vpu_data_s vpu_data_gxtvbb = {
.module_init_table_cnt = 0,
.module_init_table = NULL,
.hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
.hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
};
@@ -1308,6 +1311,7 @@ static struct vpu_data_s vpu_data_gxl = {
.module_init_table_cnt = 0,
.module_init_table = NULL,
.hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
.hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
};
@@ -1335,6 +1339,7 @@ static struct vpu_data_s vpu_data_gxm = {
.module_init_table_cnt =
sizeof(vpu_module_init_gxm) / sizeof(struct vpu_ctrl_s),
.module_init_table = vpu_module_init_gxm,
.hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
.hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
};
@@ -1361,6 +1366,7 @@ static struct vpu_data_s vpu_data_txl = {
.module_init_table_cnt = 0,
.module_init_table = NULL,
.hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
.hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
};
@@ -1388,6 +1394,7 @@ static struct vpu_data_s vpu_data_txlx = {
.module_init_table_cnt =
sizeof(vpu_module_init_txlx) / sizeof(struct vpu_ctrl_s),
.module_init_table = vpu_module_init_txlx,
.hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
.hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_txlx,
};
@@ -1414,6 +1421,7 @@ static struct vpu_data_s vpu_data_axg = {
.module_init_table_cnt = 0,
.module_init_table = NULL,
.hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
.hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_txlx,
};
@@ -1440,6 +1448,7 @@ static struct vpu_data_s vpu_data_g12a = {
.module_init_table_cnt = 0,
.module_init_table = NULL,
.hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
.hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_txlx,
};
@@ -1466,6 +1475,7 @@ static struct vpu_data_s vpu_data_g12b = {
.module_init_table_cnt = 0,
.module_init_table = NULL,
.hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
.hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_txlx,
};
@@ -1492,6 +1502,7 @@ static struct vpu_data_s vpu_data_tl1 = {
.module_init_table_cnt = 0,
.module_init_table = NULL,
.hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
.hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_tl1,
};
@@ -1518,10 +1529,38 @@ static struct vpu_data_s vpu_data_sm1 = {
.module_init_table_cnt = 0,
.module_init_table = NULL,
.hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
.hdmi_iso_table = vpu_hdmi_iso_sm1,
.reset_table = vpu_reset_txlx,
};
static struct vpu_data_s vpu_data_tm2 = {
.chip_type = VPU_CHIP_TM2,
.chip_name = "tm2",
.clk_level_dft = CLK_LEVEL_DFT_G12A,
.clk_level_max = CLK_LEVEL_MAX_G12A,
.fclk_div_table = fclk_div_table_g12a,
.gp_pll_valid = 0,
.mem_pd_reg1_valid = 1,
.mem_pd_reg2_valid = 1,
.mem_pd_reg3_valid = 1,
.mem_pd_reg4_valid = 1,
.mem_pd_table_cnt =
sizeof(vpu_mem_pd_tm2) / sizeof(struct vpu_ctrl_s),
.clk_gate_table_cnt =
sizeof(vpu_clk_gate_g12a) / sizeof(struct vpu_ctrl_s),
.mem_pd_table = vpu_mem_pd_tm2,
.clk_gate_table = vpu_clk_gate_g12a,
.module_init_table_cnt = 0,
.module_init_table = NULL,
.hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
.hdmi_iso_table = vpu_hdmi_iso_sm1,
.reset_table = vpu_reset_tl1,
};
static const struct of_device_id vpu_of_table[] = {
{
.compatible = "amlogic, vpu-gxbb",
@@ -1567,6 +1606,10 @@ static const struct of_device_id vpu_of_table[] = {
.compatible = "amlogic, vpu-sm1",
.data = &vpu_data_sm1,
},
{
.compatible = "amlogic, vpu-tm2",
.data = &vpu_data_tm2,
},
{},
};

2
drivers/amlogic/media/common/vpu/vpu.h
View File

@@ -37,6 +37,7 @@ enum vpu_chip_e {
VPU_CHIP_G12B,
VPU_CHIP_TL1,
VPU_CHIP_SM1,
VPU_CHIP_TM2,
VPU_CHIP_MAX,
};
@@ -89,6 +90,7 @@ struct vpu_data_s {
unsigned int module_init_table_cnt;
struct vpu_ctrl_s *module_init_table;
struct vpu_ctrl_s *hdmi_iso_pre_table;
struct vpu_ctrl_s *hdmi_iso_table;
struct vpu_reset_s *reset_table;
};

71
drivers/amlogic/media/common/vpu/vpu_ctrl.h
View File

@@ -379,7 +379,7 @@ static struct vpu_ctrl_s vpu_mem_pd_tl1[] = {
{VPU_VENCP, HHI_VPU_MEM_PD_REG1, 0x3, 20, 2},
{VPU_VENCL, HHI_VPU_MEM_PD_REG1, 0x3, 22, 2},
{VPU_VENCI, HHI_VPU_MEM_PD_REG1, 0x3, 24, 2},
{VPU_LS_STTS, HHI_VPU_MEM_PD_REG1, 0x3, 26, 2},
{VPU_LC_STTS, HHI_VPU_MEM_PD_REG1, 0x3, 26, 2},
{VPU_LDIM_STTS, HHI_VPU_MEM_PD_REG1, 0x3, 28, 2},
{VPU_VD2_OSD2_SCALE, HHI_VPU_MEM_PD_REG1, 0x3, 30, 2},
{VPU_VIU_WM, HHI_VPU_MEM_PD_REG2, 0x3, 0, 2},
@@ -434,7 +434,7 @@ static struct vpu_ctrl_s vpu_mem_pd_sm1[] = {
{VPU_VENCP, HHI_VPU_MEM_PD_REG1, 0x3, 20, 2},
{VPU_VENCL, HHI_VPU_MEM_PD_REG1, 0x3, 22, 2},
{VPU_VENCI, HHI_VPU_MEM_PD_REG1, 0x3, 24, 2},
{VPU_LS_STTS, HHI_VPU_MEM_PD_REG1, 0x3, 26, 2},
{VPU_LC_STTS, HHI_VPU_MEM_PD_REG1, 0x3, 26, 2},
{VPU_LDIM_STTS, HHI_VPU_MEM_PD_REG1, 0x3, 28, 2},
{VPU_VD2_OSD2_SCALE, HHI_VPU_MEM_PD_REG1, 0x3, 30, 2},
{VPU_VIU_WM, HHI_VPU_MEM_PD_REG2, 0x3, 0, 2},
@@ -449,7 +449,7 @@ static struct vpu_ctrl_s vpu_mem_pd_sm1[] = {
{VPU_DS, HHI_VPU_MEM_PD_REG2, 0x3, 18, 2},
{VPU_LUT3D, HHI_VPU_MEM_PD_REG2, 0x3, 20, 2},
{VPU_VIU2, HHI_VPU_MEM_PD_REG2, 0x3, 22, 2},
{VPU_DI_PRE, HHI_VPU_MEM_PD_REG2, 0xf, 24, 4},
{VPU_DI_PRE, HHI_VPU_MEM_PD_REG2, 0x3, 24, 2},
{VPU_RDMA, HHI_VPU_MEM_PD_REG2, 0x3, 30, 2},
{VPU_TCON, HHI_VPU_MEM_PD_REG3_SM1, 0x3, 0, 16},
{VPU_TCON, HHI_VPU_MEM_PD_REG3_SM1, 0x3, 16, 16},
@@ -458,6 +458,62 @@ static struct vpu_ctrl_s vpu_mem_pd_sm1[] = {
{VPU_MOD_MAX, VPU_REG_END, 0, 0, 0},
};
static struct vpu_ctrl_s vpu_mem_pd_tm2[] = {
/* vpu module, reg, val, bit, len */
{VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0x3, 0, 2},
{VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 0x3, 2, 2},
{VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 0x3, 4, 2},
{VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 0x3, 6, 2},
{VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 0x3, 8, 2},
{VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 0x3, 10, 2},
{VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 12, 2},
{VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 14, 2},
{VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 0x3, 16, 2},
{VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 0x3, 18, 2},
{VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 0x3, 20, 2},
{VPU_AFBC_DEC1, HHI_VPU_MEM_PD_REG0, 0x3, 22, 2},
{VPU_VIU_DI_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 24, 2},
{VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 0x3, 26, 2},
{VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 0x3, 28, 2},
{VPU_SHARP, HHI_VPU_MEM_PD_REG0, 0x3, 30, 2},
{VPU_VIU2, HHI_VPU_MEM_PD_REG1, 0xf, 0, 4},
{VPU_VKSTONE, HHI_VPU_MEM_PD_REG1, 0x3, 4, 2},
{VPU_DOLBY_CORE3, HHI_VPU_MEM_PD_REG1, 0x3, 6, 2},
{VPU_DOLBY0, HHI_VPU_MEM_PD_REG1, 0x3, 8, 2},
{VPU_DOLBY1A, HHI_VPU_MEM_PD_REG1, 0x3, 10, 2},
{VPU_DOLBY1B, HHI_VPU_MEM_PD_REG1, 0x3, 12, 2},
{VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 0x3, 14, 2},
{VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 0x3, 16, 2},
{VPU_VD2_SCALE, HHI_VPU_MEM_PD_REG1, 0x3, 18, 2},
{VPU_VENCP, HHI_VPU_MEM_PD_REG1, 0x3, 20, 2},
{VPU_VENCL, HHI_VPU_MEM_PD_REG1, 0x3, 22, 2},
{VPU_VENCI, HHI_VPU_MEM_PD_REG1, 0x3, 24, 2},
{VPU_LC_STTS, HHI_VPU_MEM_PD_REG1, 0x3, 26, 2},
{VPU_LDIM_STTS, HHI_VPU_MEM_PD_REG1, 0x3, 28, 2},
{VPU_VD2_OSD2_SCALE, HHI_VPU_MEM_PD_REG1, 0x3, 30, 2},
{VPU_VIU_WM, HHI_VPU_MEM_PD_REG2, 0x3, 0, 2},
{VPU_TCON, HHI_VPU_MEM_PD_REG2, 0x3, 2, 2},
{VPU_VIU_OSD3, HHI_VPU_MEM_PD_REG2, 0x3, 4, 2},
{VPU_VIU_OSD4, HHI_VPU_MEM_PD_REG2, 0x3, 6, 2},
{VPU_MAIL_AFBCD, HHI_VPU_MEM_PD_REG2, 0x3, 8, 2},
{VPU_VD1_SCALE, HHI_VPU_MEM_PD_REG2, 0x3, 10, 2},
{VPU_OSD_BLD34, HHI_VPU_MEM_PD_REG2, 0x3, 12, 2},
{VPU_PRIME_DOLBY_RAM, HHI_VPU_MEM_PD_REG2, 0x3, 14, 2},
{VPU_VD2_OFIFO, HHI_VPU_MEM_PD_REG2, 0x3, 16, 2},
{VPU_DS, HHI_VPU_MEM_PD_REG2, 0x3, 18, 2},
{VPU_LUT3D, HHI_VPU_MEM_PD_REG2, 0x3, 20, 2},
{VPU_DI_PRE, HHI_VPU_MEM_PD_REG2, 0x3, 24, 2},
{VPU_DOLBY_S0, HHI_VPU_MEM_PD_REG2, 0x3, 26, 2},
{VPU_DOLBY_S1, HHI_VPU_MEM_PD_REG2, 0x3, 28, 2},
{VPU_RDMA, HHI_VPU_MEM_PD_REG2, 0x3, 30, 2},
{VPU_TCON, HHI_VPU_MEM_PD_REG3, 0x3, 0, 16},
{VPU_TCON, HHI_VPU_MEM_PD_REG3, 0x3, 16, 16},
{VPU_AXI_WR1, HHI_VPU_MEM_PD_REG4, 0x3, 0, 2},
{VPU_AXI_WR0, HHI_VPU_MEM_PD_REG4, 0x3, 2, 2},
{VPU_DMA, HHI_VPU_MEM_PD_REG4, 0xf, 4, 4},
{VPU_MOD_MAX, VPU_REG_END, 0, 0, 0},
};
/* ******************************************************* */
/* VPU clock gate table */
/* ******************************************************* */
@@ -632,6 +688,15 @@ static struct vpu_ctrl_s vpu_clk_gate_g12a[] = {
{VPU_MAX, VPU_REG_END, 0, 0, 0},
};
/* ******************************************************* */
/* VPU_HDMI ISO pre: before reset */
/* ******************************************************* */
static struct vpu_ctrl_s vpu_hdmi_iso_pre_gxb[] = {
/* reg, val, bit, len */
{AO_RTI_GEN_PWR_SLEEP0, 1, 8, 1},
{VPU_REG_END, 0, 0, 0},
};
/* ******************************************************* */
/* VPU_HDMI ISO */
/* ******************************************************* */

3
drivers/amlogic/media/common/vpu/vpu_module.h
View File

@@ -78,11 +78,14 @@ static char *vpu_mod_table[] = {
"ds",
"lut3d",
"viu2_osd_rotation",
"dolby_s0",
"dolby_s1",
"rdma",
"axi_wr1",
"axi_wr0",
"afbce",
"dma"
"vpu_mod_max",

77
drivers/amlogic/media/common/vpu/vpu_power_init.c
View File

@@ -44,6 +44,7 @@ void vpu_module_init_config(void)
cnt = vpu_conf.data->module_init_table_cnt;
ctrl_table = vpu_conf.data->module_init_table;
if (ctrl_table) {
i = 0;
while (i < cnt) {
if (ctrl_table[i].reg == VPU_REG_END)
break;
@@ -71,17 +72,32 @@ void vpu_power_on(void)
{
struct vpu_ctrl_s *ctrl_table;
struct vpu_reset_s *reset_table;
unsigned int _reg, _bit, _len, mask;
unsigned int _reg, _val, _bit, _len, mask;
int i = 0, cnt;
VPUPR("vpu_power_on\n");
vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 0, 8, 1); /* [8] power on */
/* power on VPU_HDMI ISO */
ctrl_table = vpu_conf.data->hdmi_iso_pre_table;
if (ctrl_table) {
i = 0;
while (i < VPU_HDMI_ISO_CNT_MAX) {
if (ctrl_table[i].reg == VPU_REG_END)
break;
_reg = ctrl_table[i].reg;
_val = 0;
_bit = ctrl_table[i].bit;
_len = ctrl_table[i].len;
vpu_ao_setb(_reg, _val, _bit, _len);
i++;
}
}
udelay(20);
/* power up memories */
cnt = vpu_conf.data->mem_pd_table_cnt;
ctrl_table = vpu_conf.data->mem_pd_table;
i = 0;
while (i < cnt) {
if (ctrl_table[i].vmod == VPU_MOD_MAX)
break;
@@ -125,15 +141,18 @@ void vpu_power_on(void)
/* Remove VPU_HDMI ISO */
ctrl_table = vpu_conf.data->hdmi_iso_table;
i = 0;
while (i < VPU_HDMI_ISO_CNT_MAX) {
if (ctrl_table[i].reg == VPU_REG_END)
break;
_reg = ctrl_table[i].reg;
_bit = ctrl_table[i].bit;
_len = ctrl_table[i].len;
vpu_ao_setb(_reg, 0, _bit, _len);
i++;
if (ctrl_table) {
i = 0;
while (i < VPU_HDMI_ISO_CNT_MAX) {
if (ctrl_table[i].reg == VPU_REG_END)
break;
_reg = ctrl_table[i].reg;
_val = 0;
_bit = ctrl_table[i].bit;
_len = ctrl_table[i].len;
vpu_ao_setb(_reg, _val, _bit, _len);
i++;
}
}
if (vpu_debug_print_flag)
@@ -151,15 +170,18 @@ void vpu_power_off(void)
/* Power down VPU_HDMI */
/* Enable Isolation */
ctrl_table = vpu_conf.data->hdmi_iso_table;
while (i < VPU_HDMI_ISO_CNT_MAX) {
if (ctrl_table[i].reg == VPU_REG_END)
break;
_reg = ctrl_table[i].reg;
_val = ctrl_table[i].val;
_bit = ctrl_table[i].bit;
_len = ctrl_table[i].len;
vpu_ao_setb(_reg, _val, _bit, _len);
i++;
if (ctrl_table) {
i = 0;
while (i < VPU_HDMI_ISO_CNT_MAX) {
if (ctrl_table[i].reg == VPU_REG_END)
break;
_reg = ctrl_table[i].reg;
_val = ctrl_table[i].val;
_bit = ctrl_table[i].bit;
_len = ctrl_table[i].len;
vpu_ao_setb(_reg, _val, _bit, _len);
i++;
}
}
udelay(20);
@@ -188,7 +210,20 @@ void vpu_power_off(void)
udelay(20);
/* Power down VPU domain */
vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 1, 8, 1); /* PDN */
ctrl_table = vpu_conf.data->hdmi_iso_pre_table;
if (ctrl_table) {
i = 0;
while (i < VPU_HDMI_ISO_CNT_MAX) {
if (ctrl_table[i].reg == VPU_REG_END)
break;
_reg = ctrl_table[i].reg;
_val = ctrl_table[i].val;
_bit = ctrl_table[i].bit;
_len = ctrl_table[i].len;
vpu_ao_setb(_reg, _val, _bit, _len);
i++;
}
}
vpu_hiu_setb(HHI_VAPBCLK_CNTL, 0, 8, 1);
vpu_hiu_setb(HHI_VPU_CLK_CNTL, 0, 8, 1);